New patch to review for coreboot: mainboard/google/reef: consolidate gpio related defines to one place
Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16421
-gerrit
commit ee63fd7c8b5c958d4ff1d8bb61687ea78d1f2869 Author: Aaron Durbin adurbin@chromium.org Date: Fri Sep 2 17:41:58 2016 -0500
mainboard/google/reef: consolidate gpio related defines to one place
Since multiple boards will be living within one directory move all the macros for defining anyting related to GPIOs to the gpio.h header file. That way, when other boards land they can override or use them as is.
BUG=chrome-os-partner:56677
Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/reef/chromeos.c | 4 --- .../reef/variants/baseboard/include/baseboard/ec.h | 17 ------------- .../variants/baseboard/include/baseboard/gpio.h | 29 +++++++++++++++++++--- 3 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index ea0f68e..7d7af9e 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -18,12 +18,8 @@ #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> -#include <variant/ec.h> #include <variant/gpio.h>
-#define GPIO_PCH_WP GPIO_75 -#define GPIO_EC_IN_RW GPIO_41 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 5c8e306..9c8549d 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -18,23 +18,6 @@
#include <ec/google/chromeec/ec_commands.h>
-/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 - -/* EC SMI */ -#define EC_SMI_GPI GPIO_49 - -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 - #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index 2f49123..65ade88 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -19,13 +19,34 @@ #include <soc/gpio.h>
/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 + +/* EC SMI */ +#define EC_SMI_GPI GPIO_49 + +/* + * On lidopen/lidclose GPIO_22 from North Community gets toggled and + * is used in _PRW to wake up device from sleep. GPIO_22 maps to + * group GPIO_GPE_N_31_0 and the pad is configured as SCI with + * EDGE_SINGLE and INVERT. + */ +#define GPE_EC_WAKE GPE0_DW1_22 + +/* Write Protect and indication if EC is in RW code. */ +#define GPIO_PCH_WP GPIO_75 +#define GPIO_EC_IN_RW GPIO_41 + +/* * The proto boards didn't have memory SKU pins, but the same ones can be * utilized as post proto boards because the pins used were never connected * or no peripheral utilized the signals on proto boards. */ -#define MEM_CONFIG3 GPIO_45 -#define MEM_CONFIG2 GPIO_38 -#define MEM_CONFIG1 GPIO_102 -#define MEM_CONFIG0 GPIO_101 +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101
#endif /* BASEBOARD_GPIO_H */
-
Aaron Durbin