[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71277 )

Change subject: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe
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mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe

winterhold/whiterun has different H/W topology to skyrim that the eMMC device
is on a different GPP:
skyrim: GPP1 -> SD
winterhold : GPP1 -> eMMC

BUG=b:263763288
BRANCH=none
TEST=s0i3 stress over 2500 cycles.

Signed-off-by: Chris.Wang 
Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277
Tested-by: build bot (Jenkins) 
Reviewed-by: Dtrain Hsu 
Reviewed-by: Martin Roth 
---
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
1 file changed, 38 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Dtrain Hsu: Looks good to me, but someone else must approve
  Martin Roth: Looks good to me, approved

diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 9d226f1..1d50bd5 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -99,6 +99,21 @@
    register "stt_skin_temp_apu_F" = "0x3200"

device domain 0 on
+		device ref gpp_bridge_1 on
+			# Required so the NVMe gets placed into D3 when entering S0i3.
+			chip drivers/pcie/rtd3/device
+				register "name" = ""NVME""
+				device pci 00.0 on end
+			end
+		end # eMMC
+		device ref gpp_bridge_2 on
+			# Required so the NVMe gets placed into D3 when entering S0i3.
+			chip drivers/pcie/rtd3/device
+				register "name" = ""NVME""
+				device pci 00.0 on end
+			end
+		end # NVMe
+
    	device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		device ref xhci_1 on # XHCI1 controller
    			chip drivers/usb/acpi