Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19835 )
Change subject: google/kahlee: Add ChromeOS and ChromeEC ......................................................................
google/kahlee: Add ChromeOS and ChromeEC
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo.
The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas.
There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones marcj303@gmail.com --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Makefile.inc A src/mainboard/google/kahlee/bootblock.c A src/mainboard/google/kahlee/chromeos.c A src/mainboard/google/kahlee/chromeos.fmd A src/mainboard/google/kahlee/ec.c A src/mainboard/google/kahlee/ec.h M src/mainboard/google/kahlee/mainboard.c 8 files changed, 257 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/19835/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index ee97832..859b3ab 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -18,12 +18,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_AMD_STONEYRIDGE_FT4 + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 select GFXUMA + select MAINBOARD_HAS_CHROMEOS select STONEYRIDGE_UART
config MAINBOARD_DIR @@ -50,4 +53,12 @@ bool default y
+config VBOOT + select VBOOT_MOCK_SECDATA + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + +config CHROMEOS + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + endif # BOARD_GOOGLE_KAHLEE diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 87a46df..f21b0b6 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -14,10 +14,18 @@ #
bootblock-y += BiosCallOuts.c +bootblock-y += bootblock.c +bootblock-y += ec.c bootblock-y += OemCustomize.c
romstage-y += BiosCallOuts.c +romstage-y += chromeos.c romstage-y += OemCustomize.c
ramstage-y += BiosCallOuts.c +ramstage-y += chromeos.c +ramstage-y += ec.c ramstage-y += OemCustomize.c + +verstage-y += chromeos.c +verstage-y += ec.c diff --git a/src/mainboard/google/kahlee/bootblock.c b/src/mainboard/google/kahlee/bootblock.c new file mode 100644 index 0000000..a6161e4 --- /dev/null +++ b/src/mainboard/google/kahlee/bootblock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <ec.h> + +void bootblock_mainboard_init(void) +{ + /* Enable the EC as soon as we have visibility */ + mainboard_ec_init(); +} diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c new file mode 100644 index 0000000..f84c618 --- /dev/null +++ b/src/mainboard/google/kahlee/chromeos.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <vendorcode/google/chromeos/chromeos.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> + + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/kahlee/chromeos.fmd b/src/mainboard/google/kahlee/chromeos.fmd new file mode 100644 index 0000000..52aa37e --- /dev/null +++ b/src/mainboard/google/kahlee/chromeos.fmd @@ -0,0 +1,36 @@ +FLASH@0xff800000 0x800000 { +SI_ALL@0x0 0xCB000 { + UNUSED@0x00000 0x20000 + AMD_FW@0x20000 0xAB000 + } +SI_BIOS@0xCB000 0x735000 { + RW_SECTION_A@0x0 0x21e000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x20DFC0 + RW_FWID_A@0x21dfc0 0x40 + } + RW_SECTION_B@0x21e000 0x21e000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x20DFC0 + RW_FWID_B@0x21dfc0 0x40 + } + RW_MRC_CACHE@0x43C000 0x10000 + RW_ELOG@0x44C000 0x4000 + RW_SHARED@0x450000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x454000 0x2000 + RW_UNUSED@0x456000 0x4F000 +# RW_LEGACY(CBFS)@0x200000 0x200000 + WP_RO@0x4A5000 0x290000 { + RO_SECTION@0x00000 0x290000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x70000 + COREBOOT(CBFS)@0x80000 0x210000 + } + } + } +} diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c new file mode 100644 index 0000000..da0f855 --- /dev/null +++ b/src/mainboard/google/kahlee/ec.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include "ec.h" +#include <rules.h> +#include <soc/hudson.h> + +static void ramstage_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} + +static void early_ec_init(void) +{ +#ifdef __PRE_RAM__ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * -- set by hudson_lpc_decode() in pre + * - ChromeEC specific communication I/O ports. + */ + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + printk(BIOS_DEBUG, + "LPC Setup google_chromeec_ioport_range: %04x, %08zx\n", + ec_ioport_base, ec_ioport_size); + lpc_wideio_512_window(ec_ioport_base); +#endif //_PRE_RAM_ +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else + early_ec_init(); +} diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h new file mode 100644 index 0000000..bf4e3ad --- /dev/null +++ b/src/mainboard/google/kahlee/ec.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ +#define EC_SCI_GPI 24 +/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 23 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#endif diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index c07dd92..1150a3c 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <agesawrapper.h> #include <amd_pci_util.h> +#include <ec.h>
/*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -78,7 +79,7 @@
/************************************************* - * enable the dedicated function in kahlee board. + * Dedicated mainboard function *************************************************/ static void kahlee_enable(device_t dev) { @@ -86,6 +87,8 @@
/* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + mainboard_ec_init(); }
struct chip_operations mainboard_ops = {
-
Marc Jones (Code Review)