Change in ...coreboot[master]: mb/google/sarien: Add settings for noise mitgation

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30448

Change subject: mb/google/sarien: Add settings for noise mitgation
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mb/google/sarien: Add settings for noise mitgation

Enable acoustic noise mitgation for sarien platform, the slow slew rates
are fast time dived by 8.

Signed-off-by: Lijian Zhao 
Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28
---
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30448/1

diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 47abadc..0b8e5c6 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -33,6 +33,11 @@
    register "dptf_enable" = "1"
    register "dmipwroptimize" = "1"
    register "satapwroptimize" = "1"
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRateForIa" = "2"
+	register "SlowSlewRateForGt" = "2"
+	register "SlowSlewRateForSa" = "2"
+	register "SlowSlewRateForFivr" = "2"

# Intel Common SoC Config
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port