Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH

[Usha P (Code Review)]

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Subrata Banik, Angel Pons, Krishna P Bhat D, Patrick Rudolph, Kangheui Won.
Hello build bot (Jenkins), Reka Norman, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59752

to look at the new patch set (#5).

Change subject: soc/intel/alderlake: Add support for ADL-N PCH
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soc/intel/alderlake: Add support for ADL-N PCH

Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and
use it to specify the correct amount of PCIe I/O.

Document number 645550 indicates that Alder Lake-N has
12 PCH root ports and no CPU root ports.

Document number 645548 indicates ADL-N has 5 clock sources
and 5 clock request signals.

Signed-off-by: Usha P 
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
2 files changed, 12 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59752/5