[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling

[Angel Pons (Code Review)]

Attention is currently required from: Jamie Ryu, Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Ivy Jian, Arthur Heymans, Lean Sheng Tan, Eric Lai, Raj Astekar.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 )

Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> > This seems like a bug in depthcharge then, as it seems to be making an assumption about the state of the HW (i.e. BM bit set) before it uses it? If depthcharge is using DMA then IMHO it is responsible for configuring it correctly, including setting BM.
>
> Isn't that the case with depthcharge always? I remember one issue in CML days with SATA when FSP missed to configure the BM and we were seeing booting issue. Finally, we are seeing the similar issue in MTL again with IGD. Its better we configure required setting in coreboot being independent of FSP is my intention here.

We should consider the option of "why not just fix depthcharge" as well. That being said, if depthcharge doesn't "know" that this BM bit is not set (e.g. depthcharge tries to use the framebuffer through the info in coreboot tables and doesn't touch the PCI device), then I'd say coreboot should enable BM. However, in the case of SATA controllers, payloads often scan PCI devices to find SATA controllers, so setting the BM bit on these SATA controllers is the payload's responsibility.