Change in coreboot[master]: util: add DDR4 generic spd for H5ANAG6NCJR-XNC

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: add DDR4 generic spd for H5ANAG6NCJR-XNC
......................................................................

util: add DDR4 generic spd for H5ANAG6NCJR-XNC

Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro 
---
A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
3 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45962/1

diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
new file mode 100644
index 0000000..1ce7c21
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00
+00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
+F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
[phone] 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
index 202f173..21565c6 100644
--- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
@@ -13,3 +13,4 @@
 H5AN8G6NCJR-XNC,ddr4-spd-1.hex
 K4AAG165WA-BCTD,ddr4-spd-8.hex
 H5ANAG6NDMR-XNC,ddr4-spd-2.hex
+H5ANAG6NCJR-XNC,ddr4-spd-9.hex
diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
index 776bce7..72b0ccd 100644
--- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
+++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
@@ -191,6 +191,18 @@
                 "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
+        },
+        {
+            // Datasheet Revision: Rev. 1.4, May. 2020
+            "name": "H5ANAG6NCJR-XNC",
+            "attribs": {
+                "speedMTps": 3200,
+                "CL_nRCD_nRP": 22,
+                "capacityPerDieGb": 16,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
         }
     ]
 }

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: add DDR4 generic spd for H5ANAG6NCJR-XNC
......................................................................

Patch Set 1:

This is based on information from the data sheet provided in https://buganizer.corp.google.com/issues/161772961#comment52.

Please pay close attention to the following as I'm not 100% sure it's correct:

1) I assumed single-die as the doc did not appear to be specific about die count (I assumed 1 given this comment on page 33: "This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here" and the lack of any other clues when searching the datasheet for "die")

2) I assumed ranks per package is 1, as searches for rank and chip select / CS did not find any information, and Figure 1 on page 15 only shows on CS pin.

NOTE that I did confirm that the SPD file included in comment #52 linked above also has the part configured as single-die, single rank.

[Rob Barnes (Code Review)]

Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: add DDR4 generic spd for H5ANAG6NCJR-XNC
......................................................................

Patch Set 1: Code-Review+1
> Patch Set 1:
>
> This is based on information from the data sheet provided in https://buganizer.corp.google.com/issues/161772961#comment52.
>
> Please pay close attention to the following as I'm not 100% sure it's correct:
>
> I assumed single-die as the doc did not appear to be specific about die count (I assumed 1 given this comment on page 33: "This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here" and the lack of any other clues when searching the datasheet for "die")
>
> I assumed ranks per package is 1, as searches for rank and chip select / CS did not find any information, and Figure 1 on page 15 only shows on CS pin.
>
> NOTE that I did confirm that the SPD file included in comment #52 linked above also has the part configured as single-die, single rank.

Decoding the Hynix part number is a good sanity check. Here's the reference: https://drive.google.com/file/d/10JIIP46tyoFTmf4YbNAslKA7AA4vHnQZ/view?usp=s...

The 'J' denotes SDP. The J is the only difference between this and the H5ANAG6NCMR-XNC part number already listed. This new entry only differs by diesPerPackage and capacityPerDieGb, which makes sense.

Change in coreboot[master]: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

[Nick Vaccaro (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Rob Barnes, Nick Chen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45962

to look at the new patch set (#2).

Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
......................................................................

util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro 
---
A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
3 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45962/2

Change in coreboot[master]: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
......................................................................

Patch Set 2:
> Patch Set 1: Code-Review+1
> > Patch Set 1:
> >
> > This is based on information from the data sheet provided in https://buganizer.corp.google.com/issues/161772961#comment52.
> >
> > Please pay close attention to the following as I'm not 100% sure it's correct:
> >
> > I assumed single-die as the doc did not appear to be specific about die count (I assumed 1 given this comment on page 33: "This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here" and the lack of any other clues when searching the datasheet for "die")
> >
> > I assumed ranks per package is 1, as searches for rank and chip select / CS did not find any information, and Figure 1 on page 15 only shows on CS pin.
> >
> > NOTE that I did confirm that the SPD file included in comment #52 linked above also has the part configured as single-die, single rank.
>
> Decoding the Hynix part number is a good sanity check. Here's the reference: https://drive.google.com/file/d/10JIIP46tyoFTmf4YbNAslKA7AA4vHnQZ/view?usp=s...
>
> The 'J' denotes SDP. The J is the only difference between this and the H5ANAG6NCMR-XNC part number already listed. This new entry only differs by diesPerPackage and capacityPerDieGb, which makes sense.

Thanks for the pointer, Rob !

Change in coreboot[master]: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
......................................................................

Patch Set 2: Code-Review+2

Change in coreboot[master]: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
......................................................................

Patch Set 2:
> Patch Set 1:
>
> This is based on information from the data sheet provided in https://buganizer.corp.google.com/issues/161772961#comment52.
>
> Please pay close attention to the following as I'm not 100% sure it's correct:
>
> I assumed single-die as the doc did not appear to be specific about die count (I assumed 1 given this comment on page 33: "This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here" and the lack of any other clues when searching the datasheet for "die")
>
> I assumed ranks per package is 1, as searches for rank and chip select / CS did not find any information, and Figure 1 on page 15 only shows on CS pin.
>
> NOTE that I did confirm that the SPD file included in comment #52 linked above also has the part configured as single-die, single rank.

For the die count, I typically look at the # of ZQ pins.

Change in coreboot[master]: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45962 )

Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
......................................................................

util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC

Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
3 files changed, 45 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
new file mode 100644
index 0000000..1ce7c21
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00
+00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
+F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
[phone] 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
index 202f173..21565c6 100644
--- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
@@ -13,3 +13,4 @@
 H5AN8G6NCJR-XNC,ddr4-spd-1.hex
 K4AAG165WA-BCTD,ddr4-spd-8.hex
 H5ANAG6NDMR-XNC,ddr4-spd-2.hex
+H5ANAG6NCJR-XNC,ddr4-spd-9.hex
diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
index 776bce7..72b0ccd 100644
--- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
+++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
@@ -191,6 +191,18 @@
                 "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
+        },
+        {
+            // Datasheet Revision: Rev. 1.4, May. 2020
+            "name": "H5ANAG6NCJR-XNC",
+            "attribs": {
+                "speedMTps": 3200,
+                "CL_nRCD_nRP": 22,
+                "capacityPerDieGb": 16,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
         }
     ]
 }