Change in coreboot[master]: soc/intel/icelake: Use ACPI timer config from soc common code

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36931 )

Change subject: soc/intel/icelake: Use ACPI timer config from soc common code
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soc/intel/icelake: Use ACPI timer config from soc common code

Replace the usage of structure member "PMTimerDisabled" of struct
"soc_intel_icelake_config" in soc code with ACPI timer config
defined under soc/intel/common/block/timer/Kconfig.

BUG=none
TEST=none

Change-Id: I42fcf23524889d47f4491fad672ca6b3587ab348
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/finalize.c
3 files changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/36931/1

diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 4089679..8bed0b9 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -172,7 +172,7 @@

config_t *config = config_of_soc();

-	if (!config->PmTimerDisabled) {
+	if (CONFIG_ENABLE_ACPI_PM_TIMER) {
    	fadt->pm_tmr_blk = pmbase + PM1_TMR;
    	fadt->pm_tmr_len = 4;
    	fadt->x_pm_tmr_blk.space_id = 1;
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index ec625a0..21b21f7 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -207,8 +207,6 @@
    /* Enable C6 DRAM */
    uint8_t enable_c6dram;

-	uint8_t PmTimerDisabled;
-
    /* Desired platform debug type. */
    enum {
    	DebugConsent_Disabled,
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index a70b5a1..882babd 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -85,7 +85,7 @@
     */
    config = config_of_soc();
    pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
+	if (!CONFIG_ENABLE_ACPI_PM_TIMER) {
    	reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
    	reg8 |= (1 << 1);
    	write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);

[Meera Ravindranath (Code Review)]

Meera Ravindranath has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36931 )

Change subject: soc/intel/icelake: Use ACPI timer config from soc common code
......................................................................

Abandoned

Merging this commit into 36064