Patch merged into coreboot/master: amd/mct/ddr3: Rework memory speed to clock value conversion logic

the following patch was just integrated into master:
commit 6f9468f019239af70c20de9fca411fc76a00db1b
Author: Timothy Pearson 
Date:   Mon Jan 9 14:27:09 2017 -0600

amd/mct/ddr3: Rework memory speed to clock value conversion logic

The existing DRAM clock speed to configuration value logic contained
    an error resulting in a theoretical out of bounds read.  While this
    would not be hit on real hardware, it was prudent to clean up the
    logic to avoid the associated Coverity warning.

Found-by: Coverity Scan #1347353
    Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/18073
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth 
    Tested-by: Raptor Engineering Automated Test Stand 
    Reviewed-by: Paul Menzel

See https://review.coreboot.org/18073 for details.

-gerrit