Hello Frans Hendriks,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37616
to review the following change.
Change subject: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB ......................................................................
mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc.
BUG=N/A TEST=build
Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com --- M src/mainboard/portwell/m107/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37616/1
diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed..f68b071 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0"
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37616 )
Change subject: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37616 )
Change subject: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB ......................................................................
mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc.
BUG=N/A TEST=build
Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/portwell/m107/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved
diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed..f68b071 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0"
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Frans Hendriks (Code Review) -
Patrick Georgi (Code Review)
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Wim Vervoorn (Code Review)