Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings

[Gaggery Tsai (Code Review)]

Hello Kane Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/23060

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings
......................................................................

soc/intel/skylake: Override KBL-U/R IccMax settings

According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeroni/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R since device tree could not handle all
of them and it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.

+----------------+-------------+---------------+-------+-------+
| Domain/Setting |  SA         |  IA           | GTUS  |  GTS  |
+----------------+-------------+---------------+-------+-------+
| IccMax         | 6A(U42)     | 64A(U42)      | 31A   | 31A   |
|                | 4.5A(Others)| 29A(Celeron)  | 31A   | 31A   |
|                |             | 32A(i3/i5)    | 31A   | 31A   |
+----------------+-------------+---------------+-------+-------+

BUG=b:71369428
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42,
     KBL-U and Celeron SKUs are identified correctly and IccMax settings
     are passed to FSPS correctly.

Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/vr_config.c
3 files changed, 56 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/23060/2