Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55987 )

Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
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Patch Set 1:

(1 comment)

File src/soc/amd/common/block/cpu/update_microcode.c:

https://review.coreboot.org/c/coreboot/+/55987/comment/469f9335_9a5f161a 
PS1, Line 85: ucode
> If this is marked as `static` and we check if `ucode` is not NULL before performing `cbfs_map`, do y […]

On x86 `cbfs_map` returns a pointer to the MMAP SPI. i.e., It's returning the same pointer every time. So making it static doesn't actually change anything. I'm not sure how large the cache is, and if it's getting evicted, but explicitly caching it in RAM saves 30ms.