Change in coreboot[master]: soc/amd/common/block/lpc: Don't disable the HOG bit

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56233 )

Change subject: soc/amd/common/block/lpc: Don't disable the HOG bit
......................................................................

soc/amd/common/block/lpc: Don't disable the HOG bit

According to the AMD FCH architects, we should be using the default
value for the NO_HOG bit. This fixes a problem where the SPI DMA no
longer functions after the LPC init runs.

BUG=b:179699789, b:192373221
TEST=Boot guybrush and see SPI DMA working

Signed-off-by: Raul E Rangel 
Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 0 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 2586ba9..3027aae 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -61,12 +61,6 @@
    /* BIT 1 is not defined in public datasheet. */
    byte &= ~(1 << 1);

-	/*
-	 * Keep the old way. i.e., when bus master/DMA cycle is going
-	 * on on LPC, it holds PCI grant, so no LPC slave cycle can
-	 * interrupt and visit LPC.
-	 */
-	byte &= ~LPC_NOHOG;
    pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);

/*