Patch set updated for coreboot: e20f495 intel/lynxpoint: Allow to always route USB3 ports to XHCI

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6018

-gerrit

commit e20f49535c10c93171f43a8126aaba6504e681f1
Author: Stefan Reinauer 
Date:   Thu Oct 17 17:00:26 2013 -0700

intel/lynxpoint: Allow to always route USB3 ports to XHCI

This will make USB keyboards connected to USB3 ports work
    in libpayload on Beltino.

BUG=chrome-os-partner:23396
    BRANCH=none
    TEST=Use USB keyboard on Beltino in dev mode screen

Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
    Signed-off-by: Stefan Reinauer 
    Signed-off-by: Stefan Reinauer 
    Reviewed-on: https://chromium-review.googlesource.com/173640
    Reviewed-by: Duncan Laurie 
    Commit-Queue: Stefan Reinauer 
    Tested-by: Stefan Reinauer 
---
 src/southbridge/intel/lynxpoint/chip.h     | 3 +++
 src/southbridge/intel/lynxpoint/usb_xhci.c | 8 +++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index e47a031..cc2cda0 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config {
     *    [24] = CLKOUT_ITPXDP
     */
    uint32_t icc_clock_disable;
+
+	/* Route USB ports to XHCI per default */
+	uint8_t xhci_default;
 };

extern struct chip_operations southbridge_intel_lynxpoint_ops;
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 405277c..41c29f9 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -26,6 +26,8 @@
 #include <arch/io.h>
 #include "pch.h"

+typedef struct southbridge_intel_lynxpoint_config config_t;
+
 static u32 usb_xhci_mem_base(device_t dev)
 {
    u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev)
    u32 reg32;
    u16 reg16;
    u32 mem_base = usb_xhci_mem_base(dev);
+	config_t *config = dev->chip_info;

/* D20:F0:74h[1:0] = 00b (set D0 state) */
    reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
@@ -357,8 +360,11 @@ static void usb_xhci_init(device_t dev)
    	/* Reset ports that are disabled or
    	 * polling before returning to the OS. */
    	usb_xhci_reset_usb3(dev, 0);
-	}
+	} else
 #endif
+	/* Route all ports to XHCI */
+	if (config->xhci_default)
+		outb(0xca, 0xb2);
 }

static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,