Change in coreboot[master]: cpu: Add microcode at pre-defined address

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 )

Change subject: cpu: Add microcode at pre-defined address
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Patch Set 6:

(2 comments)

It'd be nice if the native coreboot code for microcode updates was tried over re-introducing blobs at fixed locations.

https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 
PS6, Line 7: c
Coreboot has native assembly code to update microcode by parsing cbfs, removing the need for microcode at a fixed location. See cpu/intel/microcode/microcode_asm.S.

https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@13 
PS6, Line 13: 
            : Also, on current version of FSP-T on Xeons microcode is not optional.
This was also observed on some older FSP1.1 versions, possibly for the same reason. https://blog.aheymans.xyz/fsp1-1-braswell-tempraminit-problems/ Might prove insightful.

Doing updates in coreboot and providing 'fake' microcode to FSP-T might also work for your use case as it did for FSP1.1 (see drivers/intel/fsp1_1/cache_as_ram.S)