Change in coreboot[master]: soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63232 )

Change subject: soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions
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soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions

According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19
and 20 is the I3C3 controller and not the I2C3 controller.

Signed-off-by: Felix Held 
Change-Id: I9688f1816aa840c64441495ed451997a474b306f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Fred Reitberger 
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/sabrina/include/soc/gpio.h
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved
  Fred Reitberger: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/sabrina/include/soc/gpio.h b/src/soc/amd/sabrina/include/soc/gpio.h
index fbb19cd..1cd72cd 100644
--- a/src/soc/amd/sabrina/include/soc/gpio.h
+++ b/src/soc/amd/sabrina/include/soc/gpio.h
@@ -148,11 +148,11 @@
 #define GPIO_18_IOMUX_GPIOxx 1
 #define GPIO_19_IOMUX_SMBUS1_SCL 0
 #define GPIO_19_IOMUX_I2C3_SCL 1
-/* GPIO 19 IOMUX == 2 is also I2C3_SCL */
+#define GPIO_19_IOMUX_I3C3_SCL 2
 #define GPIO_19_IOMUX_GPIOxx 3
 #define GPIO_20_IOMUX_SMBUS1_SDA 0
 #define GPIO_20_IOMUX_I2C3_SDA 1
-/* GPIO 19 IOMUX == 2 is also I2C3_SDA */
+#define GPIO_20_IOMUX_I3C3_SDA 2
 #define GPIO_20_IOMUX_GPIOxx 3
 #define GPIO_21_IOMUX_ESPI_RESET_L 0
 #define GPIO_21_IOMUX_KBRST_L 1