Change in coreboot[master]: AGESA f14: Factor out default MTRR settings

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

AGESA f14: Factor out default MTRR settings

All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

Tested with BUILD_TIMELESS=1, AMD Inagua remains unchanged.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons 
---
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
11 files changed, 18 insertions(+), 181 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41594/1

diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index c40ed43..781dde3 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE		CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE		CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST		&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM		0
 //#define BLDCFG_MAXIMUM_BUSNUM			0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 1d6e659..8bddb38 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-  { CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 1d6e659..8bddb38 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-  { CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 3e2f04b..0cd14d7 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -62,23 +62,6 @@
  * needed by the system.
  */

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
-  { CPU_LIST_TERMINAL }
-};
-
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER

@@ -108,7 +91,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index ebbf9c7..bbc8f00 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 39d9d7e..02a416a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -97,7 +97,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -170,23 +169,6 @@
  * needed by the system.
  */

-/* The fixed MTRR values to be set after memory initialization. */
-const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY				200 /**< DDR 400 */
 #define DDR533_FREQUENCY				266 /**< DDR 533 */
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 86fe800..eee3a4b 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -65,6 +65,23 @@
   NULL
 };

+/* The fixed MTRR values to be set after memory initialization. */
+static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+	{ AMD_AP_MTRR_FIX4k_C0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_C8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ CPU_LIST_TERMINAL },
+};
+
 /* Process solution defined socket / family installations
  *
  * As part of the release package for each image, define the options below to select the
@@ -1079,7 +1096,7 @@
 #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
   #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
 #else
-  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+  #define CFG_AP_MTRR_SETTINGS_LIST           (&OntarioApMtrrSettingsList)
 #endif

/*---------------------------------------------------------------------------

[Angel Pons (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41594

to look at the new patch set (#2).

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

AGESA f14: Factor out default MTRR settings

All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

Tested with BUILD_TIMELESS=1, AMD Inagua remains unchanged.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons 
---
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/mainboard/pcengines/apu1/buildOpts.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
12 files changed, 18 insertions(+), 199 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41594/2

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 3: Code-Review+1

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Paul Menzel, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41594

to look at the new patch set (#4).

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

AGESA f14: Factor out default MTRR settings

All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons 
---
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/mainboard/pcengines/apu1/buildOpts.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
12 files changed, 18 insertions(+), 199 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41594/4

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 4: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/41594/4/src/vendorcode/amd/agesa/f1... 
File src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h:

https://review.coreboot.org/c/coreboot/+/41594/4/src/vendorcode/amd/agesa/f1... 
PS4, Line 68: he fixed MTRR values to be set after memory initialization.
Add a comment that these are the default MTRR values?

[Krystian Hebel (Code Review)]

Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 4: Code-Review+1

[Angel Pons (Code Review)]

Hello Mike Banon, build bot (Jenkins), Michał Żygowski, Paul Menzel, Arthur Heymans, Mike Banon, Krystian Hebel, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41594

to look at the new patch set (#8).

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

AGESA f14: Factor out default MTRR settings

All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons 
---
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/mainboard/pcengines/apu1/buildOpts.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
12 files changed, 18 insertions(+), 199 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41594/8

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41594/4/src/vendorcode/amd/agesa/f1... 
File src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h:

https://review.coreboot.org/c/coreboot/+/41594/4/src/vendorcode/amd/agesa/f1... 
PS4, Line 68: he fixed MTRR values to be set after memory initialization.
> Add a comment that these are the default MTRR values?

Done

[Mike Banon (Code Review)]

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 8: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

AGESA f14: Factor out default MTRR settings

All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594
Tested-by: build bot (Jenkins) 
Reviewed-by: Mike Banon 
---
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/mainboard/pcengines/apu1/buildOpts.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
12 files changed, 18 insertions(+), 199 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mike Banon: Looks good to me, approved

diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index c40ed43..781dde3 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE		CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE		CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST		&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM		0
 //#define BLDCFG_MAXIMUM_BUSNUM			0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 1d6e659..8bddb38 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-  { CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 1d6e659..8bddb38 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-  { CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 5583a8b..1e2ebb0 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -62,23 +62,6 @@
  * needed by the system.
  */

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
-  { CPU_LIST_TERMINAL }
-};
-
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER

@@ -108,7 +91,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 //#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM                  0
 //#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index ebbf9c7..bbc8f00 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 39d9d7e..02a416a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -97,7 +97,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -170,23 +169,6 @@
  * needed by the system.
  */

-/* The fixed MTRR values to be set after memory initialization. */
-const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY				200 /**< DDR 400 */
 #define DDR533_FREQUENCY				266 /**< DDR 533 */
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 02b248f..cda2d9d 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 4780c33..5f92720 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -83,7 +83,6 @@
 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
 //#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
 #define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
 #define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
 //#define BLDCFG_STARTING_BUSNUM				0
 //#define BLDCFG_MAXIMUM_BUSNUM					0xf8
@@ -157,23 +156,6 @@
  */
 #include <AGESA.h>

-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL }
-};
-
 /* Include the files that instantiate the configuration definitions. */

#include "cpuRegisters.h"
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 86fe800..9aa9cbd 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -65,6 +65,23 @@
   NULL
 };

+/* The default fixed MTRR values to be set after memory initialization */
+static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+	{ AMD_AP_MTRR_FIX4k_C0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_C8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F0000,  0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F8000,  0x1E1E1E1E1E1E1E1Eull },
+	{ CPU_LIST_TERMINAL },
+};
+
 /* Process solution defined socket / family installations
  *
  * As part of the release package for each image, define the options below to select the
@@ -1079,7 +1096,7 @@
 #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
   #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
 #else
-  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+  #define CFG_AP_MTRR_SETTINGS_LIST           (&OntarioApMtrrSettingsList)
 #endif

/*---------------------------------------------------------------------------

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41594 )

Change subject: AGESA f14: Factor out default MTRR settings
......................................................................

Patch Set 9:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3983
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3982
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3981
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3980

Please note: This test is under development and might not be accurate at all!