Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device

[Lijian Zhao (Code Review)]

Hello Pratikkumar V Prajapati, Subrata Banik, Kyoung Il Kim, Li1 Feng, Bora Guvendik, Hannah Williams, build bot (Jenkins), Krzysztof M Sywula,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/29274

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: Enable ISH from device
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soc/intel/cannonlake: Enable ISH from device

PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.

BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.

Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29274/3