build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )
Change subject: riscv: update misaligned memory access exception handling ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c:
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@176 PS3, Line 176: int regnum = ((insn >> match->reg_shift) & match->reg_mask) + match->reg_addition; line over 80 characters
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@184 PS3, Line 184: buff.b[i] = mprv_read_u8((uint8_t *)(tf->badvaddr + i)); line over 80 characters
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@237 PS3, Line 237: /* writing to memory by bytes prevents misaligned memory access */ line over 80 characters
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@239 PS3, Line 239: mprv_write_u8((uint8_t *)(tf->badvaddr + i), buff.b[i]); line over 80 characters
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c:
https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c@191 PS3, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'?
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build bot (Jenkins) (Code Review)