Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
lp4x: Add new memory parts and generate SPDs
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics.
Add new generic SPD lp4x-spd-6.hex based on attributes of MT53D512M64D4NW-046 WT:F.
BUG=b:172993397 TEST=none
Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- A src/soc/intel/tigerlake/spd/lp4x-spd-6.hex M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 3 files changed, 46 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47980/1
diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex new file mode 100644 index 0000000..f330d4b --- /dev/null +++ b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 00 08 00 00 00 00 02 01 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index c7e9690..3450f1f 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -16,3 +16,4 @@ H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex +MT53D512M64D4NW-046 WT:F,lp4x-spd-6.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 91062d0..7dc502e 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -217,6 +217,18 @@ "ranksPerChannel": 1, "speedMbps": 4267 } - } + }, + { + "name": "MT53D512M64D4NW-046 WT:F", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 1, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + } ] }
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 221: { looks like you have a mix of tabs and spaces for indentation.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 226: 1 Doesn't this part have 2 channels per die?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 221: {
looks like you have a mix of tabs and spaces for indentation.
Thanks, will fix it on next patch upload.
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 226: 1
Doesn't this part have 2 channels per die?
From spec: • Array configuration – 512 Meg × 64 (4 channels × 16 I/O) 512M64 • Device configuration – 512M16 × 4 die in package
I thought that breaks down to 1 channel per die.
There are only two ZQ pins, so we set diesPerPackage to 2 instead of 4. Does that mean that we need to double the channelsPerDie since we half the die count so that we still end up with a total channel count of 4 for the package?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 226: 1
From spec: […]
From JEDEC spec JESD209-4C, Figure 1, for x16 part, if 2 sets of DQ[15:0] share the same ZQ pin, then it is 2 channels per die. For the part(MT53D512M64D4NW-046 WT:F), I see that DQ[15:0]_A and DQ[15:0]_B share ZQ0_A pin. Hence, two channels per die.
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Tim Wawrzynczak, Rob Barnes, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47980
to look at the new patch set (#2).
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
lp4x: Add new memory parts and generate SPDs
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics.
BUG=b:172993397 TEST=none
Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47980/2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 221: {
Thanks, will fix it on next patch upload.
Done
https://review.coreboot.org/c/coreboot/+/47980/1/util/spd_tools/lp4x/global_... PS1, Line 226: 1
From JEDEC spec JESD209-4C, Figure 1, for x16 part, if 2 sets of DQ[15:0] share the same ZQ pin, the […]
Thanks, Furquan !
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 2: Code-Review+2
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47980 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
lp4x: Add new memory parts and generate SPDs
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics.
BUG=b:172993397 TEST=none
Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Rob Barnes robbarnes@google.com --- M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rob Barnes: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index c7e9690..f09a27f 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -16,3 +16,4 @@ H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex +MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 91062d0..ffb08c7 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -217,6 +217,18 @@ "ranksPerChannel": 1, "speedMbps": 4267 } + }, + { + "name": "MT53D512M64D4NW-046 WT:F", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] }
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Caveh Jalali (Code Review) -
Furquan Shaikh (Code Review)
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Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
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Rob Barnes (Code Review)