Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28617

Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store
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[WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store

TODO: test!
TODO: clean up

Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling")
Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845
Signed-off-by: Jonathan Neuschäfer 
---
M src/arch/riscv/misaligned.c
1 file changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28617/1

diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index cb045b8..7ac810f 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -174,11 +174,15 @@
 {
    uintptr_t insn = 0;
    union endian_buf buff;
+	bool is_compressed = false;

/* try to fetch 16/32 bits instruction */
-	if (fetch_16bit_instruction(tf->epc, &insn))
-		if (fetch_32bit_instruction(tf->epc, &insn))
+	if (fetch_16bit_instruction(tf->epc, &insn) < 0) {
+		if (fetch_32bit_instruction(tf->epc, &insn) < 0)
    		redirect_trap();
+	} else {
+		is_compressed = true;
+	}

/* matching instruction */
    struct memory_instruction_info *match = match_instruction(insn);
@@ -264,4 +268,7 @@
    		mprv_write_u8(addr, buff.b[i]);
    	}
    }
+
+	/* return to where we came from */
+	write_csr(mepc, read_csr(mepc) + is_compressed? 2:4);
 }