[XS] Change in coreboot[main]: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly

[Kane Chen (Code Review)]

Attention is currently required from: Eran Mitrani, Eric Lai, Kapil Porwal, Paul Menzel, Ravishankar Sarawadi, Tarun.

Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78252?usp=email )

Change subject: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
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Patch Set 3:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78252/comment/5a7f032a_96505cf8 :
PS2, Line 10: code requires
> … code that requires …?

Done

https://review.coreboot.org/c/coreboot/+/78252/comment/7442d190_3bb097a6 :
PS2, Line 11: insrc/soc/intel/common/acpi/pcie_clk.asl
> Missing space after *in*.

Done

https://review.coreboot.org/c/coreboot/+/78252/comment/7db91648_9079b8a0 :
PS2, Line 13: TEST=suspend_stress_test 50 cycle pass, type-c display OK on screebo
> Did it also succeed before your change?

yes, i just wanted to make sure no regression.