Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34396 )
Change subject: mb/google/hatch: Fix SD card is detected as read only issue ......................................................................
mb/google/hatch: Fix SD card is detected as read only issue
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down.
As per schematics SD host controller SD_WP pin is not connected to uSD card connector. Configured gpio pin as NF1 with internal pull down in order to overcome gpio default state in hatch which makes SoC SD_WP pin is enable.
BUG=b:137729527 BRANCH=None TEST=Able to write/read data to/from sd card after mounting card device.
Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 6c6e04b..8a0c948 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -324,8 +324,12 @@ PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, NONE), + /* G7 : SD_WP + * As per schematics SD host controller SD_WP pin is not connected to + * uSD card connector. In order to overcome gpio default state, ensures + * to configure gpio pin as NF1 with internal 20K pull down. + */ + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* * H0 : HP_INT_L */