Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior

[Ryan Salsamendi (Code Review)]

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20464

Change subject: southbridge/intel/lynxpoint: Fix undefined behavior
......................................................................

southbridge/intel/lynxpoint: Fix undefined behavior

Fix undefined behavior found by clang's -Wshift-sign-overflow, find,
and source inspection. Left shifting an int where the right operand is
> = the width of the type is undefined. Add UL suffix since it's safe

for unsigned types.

Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi 
---
M src/southbridge/intel/lynxpoint/finalize.c
M src/southbridge/intel/lynxpoint/lp_gpio.h
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
6 files changed, 11 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20464/1

diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index 1ff38e9..79a0915 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -40,7 +40,7 @@
 #endif

/* TCLOCKDN: TC Lockdown */
-	RCBA32_OR(0x0050, (1 << 31));
+	RCBA32_OR(0x0050, (1UL << 31));

/* BIOS Interface Lockdown */
    RCBA32_OR(0x3410, (1 << 0));
@@ -55,7 +55,7 @@
    pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));

/* PMSYNC */
-	RCBA32_OR(PMSYNC_CONFIG, (1 << 31));
+	RCBA32_OR(PMSYNC_CONFIG, (1UL << 31));

/* R/WO registers */
    RCBA32(0x21a4) = RCBA32(0x21a4);
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index c35e770..64e9c31 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -51,9 +51,9 @@
 #define GPI_LEVEL		(1 << 30)

#define GPO_LEVEL_SHIFT		31
-#define GPO_LEVEL_MASK		(1 << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_LOW		(0 << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_HIGH		(1 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_MASK		(1UL << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_LOW		(0UL << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_HIGH		(1UL << GPO_LEVEL_SHIFT)

/* conf1 */

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 37cd94b..b8ffeba 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -475,7 +475,7 @@
    	reg32 &= ~(1 << 29); // LPC Dynamic
    else
    	reg32 |= (1 << 29); // LPC Dynamic
-	reg32 |= (1 << 31); // LP LPC
+	reg32 |= (1UL << 31); // LP LPC
    reg32 |= (1 << 30); // LP BLA
    reg32 |= (1 << 28); // GPIO Dynamic
    reg32 |= (1 << 27); // HPET Dynamic
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d76faf7..655aef1 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -242,7 +242,7 @@
 #define GEN_PMCON_2		0xa2
 #define GEN_PMCON_3		0xa4
 #define PMIR			0xac
-#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9LOCK		(1UL << 31)
 #define  PMIR_CF9GR		(1 << 20)

/* GEN_PMCON_3 bits */
@@ -389,7 +389,7 @@
 #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
 #define  XHCI_USB3_PORTSC_LWS  	(1 << 16)	/* Link Write Strobe */
 #define  XHCI_USB3_PORTSC_PED 	(1 << 1)	/* Port Enabled/Disabled */
-#define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
+#define  XHCI_USB3_PORTSC_WPR	(1UL << 31)	/* Warm Port Reset */
 #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
 #define   XHCI_PLSR_DISABLED	(4 << 5)	/* Port is disabled */
 #define   XHCI_PLSR_RXDETECT	(5 << 5)	/* Port is disconnected */
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 3d01cd6..d58ef6d 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -188,6 +188,7 @@
    for (i = 0; i < rpc.num_ports; i++) {
    	device_t dev;
    	int rp;
+		static const uint32_t highBit = (1UL << 31);

dev = rpc.ports[i];
    	rp = root_port_number(dev);
@@ -214,7 +215,7 @@
    		}

pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
-			pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
+			pci_update_config32(dev, 0x420, ~highBit, highBit);

/* Per-Port CLKREQ# handling. */
    		if (is_lp && gpio_is_native(18 + rp - 1))
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 31081d7..c45579b 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -134,7 +134,7 @@
    	reg32 |= 1 << 18;    /* BWG step 10 */
    	reg32 |= 1 << 29;    /* BWG step 11 */
    	if (pch_is_lp()) {
-			reg32 &= ~((1 << 31) | (1 << 30));
+			reg32 &= ~((1UL << 31) | (1 << 30));
    		reg32 |= 1 << 23;
    		reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
    	}