Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42095/1
diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 2c4554d..169955c 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -52,10 +52,7 @@
/* HPG section 3.1.7.1 */ - if (protocol == SE_PROTOCOL_UART) { - /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ - clock_configure_qup(bus, QUPV3_UART_SRC_HZ); - } else { + if (protocol != SE_PROTOCOL_UART) { setbits_le32(®s->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); /* configure clock dfsr */ diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index f9d99bb..4048525 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -71,7 +71,7 @@ /* sc7180 requires 16 clock pulses to sample 1 bit of data */ uart_freq = baud_rate * 16;
- div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq); + div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); write32(®s->geni_ser_m_clk_cfg, (div << 4) | 1); write32(®s->geni_ser_s_clk_cfg, (div << 4) | 1);
@@ -147,7 +147,7 @@ serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - serial.input_hertz = QUPV3_UART_SRC_HZ; + serial.input_hertz = SRC_XO_HZ;
lb_add_serial(&serial, data); }
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@17 PS1, Line 17: done the changes was changed
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@19 PS1, Line 19: in coreboot UART driver. Please reference the version in the blobs repository.
Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@17 PS1, Line 17: done the changes
was changed
ok will change
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@19 PS1, Line 19: in coreboot UART driver.
Please reference the version in the blobs repository.
OK will update blobs version
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@20 PS1, Line 20: Sorry, I'm still a bit confused about what this patch does and why. So previously coreboot was configuring the QUP source clock to 7.3728 MHz, but now you want it at 19.2 MHz instead? I can believe that either value would work, I just don't understand why it changes now and what this had to do with QcLib?
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ If we no longer need this constant, please also remove it from clock.h. Also remove the corresponding entry from the qup_cfg array in clock.c if we don't need to support this frequency anymore.
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) { How is the QUP clock configured now if you just take this out? Shouldn't we still call
clock_configure_qup(bus, SRC_XO_HZ)
somewhere? Are you just hoping that this was already set up by PBL or something? I would prefer if coreboot does its own clock setup, even if it just writes the same values that PBL would've put in there already.
Hello build bot (Jenkins), Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42095
to look at the new patch set (#2).
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib was changed to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42095/2
Hello build bot (Jenkins), Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42095
to look at the new patch set (#3).
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib was changed to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
QcLib change blob version: BOOT.XF.3.1.c4-00015-SC7180LCB-1
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42095/3
Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@17 PS1, Line 17: done the changes
ok will change
Done
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@19 PS1, Line 19: in coreboot UART driver.
OK will update blobs version
Done
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@20 PS1, Line 20:
Sorry, I'm still a bit confused about what this patch does and why. […]
This change is w.r.t the bug https://partnerissuetracker.corp.google.com/issues/153515979 , before QcLib fix we were using the hack to configure the clock to 7.3728MHz to maintain the div=4 as per the QcLib requirement(as it reconfigures UART registers to achieve 115200 baud). Now we have QcLib fix in place, so we removed the hack.
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
How is the QUP clock configured now if you just take this out? Shouldn't we still call […]
The source clock is assumed as 19.2MHz, and for this no need to call clock_configure_qup(). We are following the same for all (SPI, UART, I2C) drivers. You want this clock_configure_qup() to be called specifically for UART driver?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@20 PS1, Line 20:
This change is w.r.t the bug https://partnerissuetracker.corp.google. […]
Ack
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
The source clock is assumed as 19.2MHz, and for this no need to call clock_configure_qup(). […]
I thought all the other QUPs (SPI and I2C) are using DFSR so their frequency settings are implicitly initialized by clock_configure_dfsr(). Is that not how it works? I thought because 19.2MHz is the first entry in the DFSR array that would somehow implicitly make it use that as the base clock if you don't set anything else? (To be fair, I never quite understood the DFSR stuff as well as I probably should, I would appreciate more explanations on that.)
So if the other QUPs get their frequency set by that, then the UART QUP should also have its frequency set explicitly somehow.
Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
I thought all the other QUPs (SPI and I2C) are using DFSR so their frequency settings are implicitly […]
Clock team, can you comment on Julius query on DFSR?
So if the other QUPs get their frequency set by that, then the UART QUP should also have its frequency set explicitly somehow.>> was informed from previous Cheza clock POC (David Dai) that no need to configure the frequency explicitly for XO.
Hello build bot (Jenkins), Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42095
to look at the new patch set (#5).
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42095/5
Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
Clock team, can you comment on Julius query on DFSR? […]
UART does not use DFSR mode, it is only SPI and I2C which uses the DFSR.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 8: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
UART does not use DFSR mode, it is only SPI and I2C which uses the DFSR.
That wasn't really the question... eh, whatever, it doesn't really matter as long as it works.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 8: -Code-Review
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
If we no longer need this constant, please also remove it from clock.h. […]
This is still open, please at least do that.
Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
This is still open, please at least do that.
ok
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
ok
*ping*
Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
That wasn't really the question... eh, whatever, it doesn't really matter as long as it works.
Hi Julius,
We have already passed CS and would like to add/fix code which are required for functionality. We want to keep such cleanups for the next project from the clock code.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
*ping*
*ping*
This is the unresolved comment.
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
Hi Julius, […]
Just to clarify, when I asked for the outstanding comments on this patch to be addressed, I was talking about the *unresolved* comment (the one on line 57 of the 'Base' side of this file diff). This comment here had already been marked resolved by me so I'm okay leaving that as is. The other comment is just about removing a constant definition that is no longer used which hopefully won't cause too much validation work.
Hello build bot (Jenkins), Julius Werner, mturney mturney, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42095
to look at the new patch set (#18).
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42095/18
Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
*ping* […]
Sure, Julius, I will upload the change.
But I remember 'QUPV3_UART_SRC_HZ' was introduced due to your earlier comments(sorry I am not able to track them back). Will remove the frequency support as well as the macro.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
Sure, Julius, I will upload the change. […]
Well yes, back when we had code here that referenced that frequency I wanted a single constant for it. Now that this code doesn't exist anymore that constant doesn't really mean anything anymore so we should remove it.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 23: Code-Review+2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 57: QUPV3_UART_SRC_HZ
Well yes, back when we had code here that referenced that frequency I wanted a single constant for i […]
Done
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi rojay@codeaurora.org Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_uart.c 2 files changed, 3 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index b5adee2..3dbe3e6 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -54,10 +54,7 @@
/* HPG section 3.1.7.1 */ - if (protocol == SE_PROTOCOL_UART) { - /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ - clock_configure_qup(bus, QUPV3_UART_SRC_HZ); - } else { + if (protocol != SE_PROTOCOL_UART) { setbits_le32(®s->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); /* configure clock dfsr */ diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index bf274c2..45d3d02 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -71,7 +71,7 @@ /* sc7180 requires 16 clock pulses to sample 1 bit of data */ uart_freq = baud_rate * 16;
- div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq); + div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); write32(®s->geni_ser_m_clk_cfg, (div << 4) | 1); write32(®s->geni_ser_s_clk_cfg, (div << 4) | 1);
@@ -147,7 +147,7 @@ serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - serial.input_hertz = QUPV3_UART_SRC_HZ; + serial.input_hertz = SRC_XO_HZ;
lb_add_serial(&serial, data); }
-
Julius Werner (Code Review) -
Paul Menzel (Code Review)
-
Ravi kumar (Code Review)
-
Roja Rani Yarubandi (Code Review)
-
Taniya Das (Code Review)