Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 163 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/1
diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 8f1e2ea..cb05019 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -219,7 +219,7 @@ {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, {EOT}}}, {0x8513, "IT8513E/F/G", { - {EOT}}}, + {EOT}}}, {0x8516, "IT8516???", { {NOLDN, "Chip ID", {0x20,0x21, EOT}, @@ -1064,6 +1064,92 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,EOT}}, {EOT}}}, + {0x8987, "IT8987", { + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x89,0x87, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x03,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Address (D2ADR)", + {0x2e,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Data (D2DAT)", + {0x2f,EOT}, + {0x00,EOT}}, + {NOLDN, "Logical Device Activate Register (LDA)", + {0x30,EOT}, + {0x00,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", + {0x60,0x61,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", + {0x62,0x63,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", + {0x70,EOT}, + {NANA,EOT}}, + {NOLDN, "Interrupt Request Type Select (IRQTP)", + {0x71,EOT}, + {NANA,EOT}}, + {NOLDN, "DMA Channel Select 0 (DMAS0)", + {0x74,EOT}, + {0x04,EOT}}, + {NOLDN, "DMA Channel Select 1 (DMAS1)", + {0x75,EOT}, + {0x04,EOT}}, + {0x04, "System Wake-Up Control (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "KBC/Mouse Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0c,0x01,EOT}}, + {0x06, "KBC/Keyboard Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x10,0x00,0x02,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x10, "Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}}, + {0x11, "Power Management I/F Channel 1 (PMC1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management I/F Channel 2 (PMC2)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x13, "Serial Peripheral Interface (SSPI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x14, "Platform Environment Control Interface (PECI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x17, "Power Management I/F Channel 3 (PMC3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x18, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x19, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {EOT}}}, {EOT} };
@@ -1280,6 +1366,68 @@ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, +{0x8987, "IT8987", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, + 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, + 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, + 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, + 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, + 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, + 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {EOT} };
@@ -1351,6 +1499,14 @@ OUTB((port == 0x2e) ? 0x55 : 0xaa, port); }
+static void enter_conf_mode_ite_it8987e(uint16_t port) +{ + OUTB(0x89, port); + OUTB(0x87, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + static void exit_conf_mode_ite(uint16_t port) { regwrite(port, 0x02, 0x02); @@ -1444,6 +1600,12 @@ if (chip_found_at_port) return;
+ enter_conf_mode_ite_it8987e(port); + probe_idregs_ite_helper("(init=it8987e) ", port); + exit_conf_mode_ite(port); + if (chip_found_at_port) + return; + enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port);
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 163 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/2
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 162 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/3
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 162 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/4
Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34888
to look at the new patch set (#5).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 162 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/5
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c File util/superiotool/ite.c:
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1068 PS5, Line 1068: {NOLDN, "Chip ID", : {0x20,0x21, EOT}, : {0x89,0x87, EOT}}, might be a bit redundant, since it's used to detect the chip. i'm not really opposed to keeping this though
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1092 PS5, Line 1092: {NOLDN, "Logical Device Activate Register (LDA)", : {0x30,EOT}, : {0x00,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", : {0x60,0x61,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", : {0x62,0x63,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", : {0x70,EOT}, : {NANA,EOT}}, : {NOLDN, "Interrupt Request Type Select (IRQTP)", : {0x71,EOT}, : {NANA,EOT}}, : {NOLDN, "DMA Channel Select 0 (DMAS0)", : {0x74,EOT}, : {0x04,EOT}}, : {NOLDN, "DMA Channel Select 1 (DMAS1)", : {0x75,EOT}, : {0x04,EOT}}, this is all specific to the different LDNs. for the NOLDN case you'd get values depending on which LDN got selected last which is nondeterministic for superiotool
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c File util/superiotool/ite.c:
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1067 PS5, Line 1067: {0x8987, "IT8987", { Minor: Maybe add a comment noting that global registers 0x24, 0x27, 0x28, 0x29, 0x2a, 0x2b are reserved (if that's not implied already by their absence)
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1092 PS5, Line 1092: {NOLDN, "Logical Device Activate Register (LDA)", : {0x30,EOT}, : {0x00,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", : {0x60,0x61,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", : {0x62,0x63,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", : {0x70,EOT}, : {NANA,EOT}}, : {NOLDN, "Interrupt Request Type Select (IRQTP)", : {0x71,EOT}, : {NANA,EOT}}, : {NOLDN, "DMA Channel Select 0 (DMAS0)", : {0x74,EOT}, : {0x04,EOT}}, : {NOLDN, "DMA Channel Select 1 (DMAS1)", : {0x75,EOT}, : {0x04,EOT}},
this is all specific to the different LDNs. […]
For context: These are specified in the datasheet as the common fields of the LDN-specific registers. So they're still LDN-specific, but you know that 0x71 means "IRQ number" everywhere (as opposed to the 0xf* registers, whose meaning is LDN-specific)
The idea is that the first registers are like a "header" and the registers for each LDN (0x30 onwards) are on different pages. You can choose between different pages using register 0x07. To get an idea of what this looks like check: Figure 6-1. Host View Register Map via Index-Data Pair
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1131 PS5, Line 1131: {0x11, "Power Management I/F Channel 1 (PMC1)", Note for reviewers: PMC1 does lack the 0x64, 0x65, 0xf0 registers that other PMCs have.
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1143 PS5, Line 1143: {0x17, "Power Management I/F Channel 3 (PMC3)", Same note as PMC1
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1149 PS5, Line 1149: 4 (PMC4 Copypasta went wrong? s/4/5/g
Hello Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34888
to look at the new patch set (#6).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 141 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/6
Matt Parnell has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
Patch Set 6:
(1 comment)
Patch Set 5:
(5 comments)
I believe patch set 7 has addressed all concerns mentioned so far; I removed the LDN specific definitions.
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c File util/superiotool/ite.c:
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1092 PS5, Line 1092: {NOLDN, "Logical Device Activate Register (LDA)", : {0x30,EOT}, : {0x00,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", : {0x60,0x61,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", : {0x62,0x63,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", : {0x70,EOT}, : {NANA,EOT}}, : {NOLDN, "Interrupt Request Type Select (IRQTP)", : {0x71,EOT}, : {NANA,EOT}}, : {NOLDN, "DMA Channel Select 0 (DMAS0)", : {0x74,EOT}, : {0x04,EOT}}, : {NOLDN, "DMA Channel Select 1 (DMAS1)", : {0x75,EOT}, : {0x04,EOT}},
For context: These are specified in the datasheet as the common fields of the LDN-specific registers […]
Which explains why other models usually leave these out...I'll fix and push shortly.
Hello Felix Held, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34888
to look at the new patch set (#7).
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 141 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/7
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
Patch Set 7: Code-Review+2
(4 comments)
since I don't have the datasheet, I can't verify the default values and the registers being present in the chip in this patch; what I could verify looked good to me in this patchset
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c File util/superiotool/ite.c:
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1067 PS5, Line 1067: {0x8987, "IT8987", {
Minor: Maybe add a comment noting that global registers 0x24, 0x27, 0x28, 0x29, 0x2a, 0x2b are reser […]
Done
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1068 PS5, Line 1068: {NOLDN, "Chip ID", : {0x20,0x21, EOT}, : {0x89,0x87, EOT}},
might be a bit redundant, since it's used to detect the chip. […]
Done
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1092 PS5, Line 1092: {NOLDN, "Logical Device Activate Register (LDA)", : {0x30,EOT}, : {0x00,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", : {0x60,0x61,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", : {0x62,0x63,EOT}, : {NANA,NANA,EOT}}, : {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", : {0x70,EOT}, : {NANA,EOT}}, : {NOLDN, "Interrupt Request Type Select (IRQTP)", : {0x71,EOT}, : {NANA,EOT}}, : {NOLDN, "DMA Channel Select 0 (DMAS0)", : {0x74,EOT}, : {0x04,EOT}}, : {NOLDN, "DMA Channel Select 1 (DMAS1)", : {0x75,EOT}, : {0x04,EOT}},
Which explains why other models usually leave these out...I'll fix and push shortly.
Done
https://review.coreboot.org/c/coreboot/+/34888/5/util/superiotool/ite.c@1149 PS5, Line 1149: 4 (PMC4
Copypasta went wrong? s/4/5/g
Done
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34888 )
Change subject: util/superiotool: add IT8987 detection and register support ......................................................................
util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell mparnell@gmail.com
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/34888 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M util/superiotool/ite.c 1 file changed, 141 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 8f1e2ea..2e21e80 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1064,6 +1064,71 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,EOT}}, {EOT}}}, + {0x8987, "IT8987", { /* global registers 0x24, 0x27, 0x28, 0x29, 0x2a, 0x2b are reserved */ + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x89,0x87, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x03,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Address (D2ADR)", + {0x2e,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Data (D2DAT)", + {0x2f,EOT}, + {0x00,EOT}}, + {0x04, "System Wake-Up Control (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "KBC/Mouse Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0c,0x01,EOT}}, + {0x06, "KBC/Keyboard Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x10,0x00,0x02,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x10, "Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}}, + {0x11, "Power Management I/F Channel 1 (PMC1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management I/F Channel 2 (PMC2)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x13, "Serial Peripheral Interface (SSPI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x14, "Platform Environment Control Interface (PECI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x17, "Power Management I/F Channel 3 (PMC3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x18, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x19, "Power Management I/F Channel 5 (PMC5)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {EOT}}}, {EOT} };
@@ -1280,6 +1345,68 @@ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, +{0x8987, "IT8987", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, + 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, + 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, + 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, + 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, + 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, + 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {EOT} };
@@ -1351,6 +1478,14 @@ OUTB((port == 0x2e) ? 0x55 : 0xaa, port); }
+static void enter_conf_mode_ite_it8987e(uint16_t port) +{ + OUTB(0x89, port); + OUTB(0x87, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + static void exit_conf_mode_ite(uint16_t port) { regwrite(port, 0x02, 0x02); @@ -1444,6 +1579,12 @@ if (chip_found_at_port) return;
+ enter_conf_mode_ite_it8987e(port); + probe_idregs_ite_helper("(init=it8987e) ", port); + exit_conf_mode_ite(port); + if (chip_found_at_port) + return; + enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port);
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Matt Parnell (Code Review)
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Patrick Georgi (Code Review)