Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31276
Change subject: [WIP] mb/google/hatch: Enable DPTF functionality ......................................................................
[WIP] mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31276/1
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 93f7fc0..e6321ba 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -59,4 +59,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..aaef663 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..5e3de83 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +#endif +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl>
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: [WIP] mb/google/hatch: Enable DPTF functionality ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31276/1//COMMIT_MSG@7 PS1, Line 7: [WIP] Is this still WIP?
Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31276
to look at the new patch set (#2).
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31276/2
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31276/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31276/1//COMMIT_MSG@7 PS1, Line 7: [WIP]
Is this still WIP?
This is ready to go now.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31276/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/#/c/31276/2/src/mainboard/google/hatch/variants/... PS2, Line 46: #ifdef DPTF_ENABLE_CHARGER Can we get rid of this? Its defined just above here.
Hello Aaron Durbin, Rajat Jain, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31276
to look at the new patch set (#3).
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31276/3
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31276/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:
https://review.coreboot.org/#/c/31276/2/src/mainboard/google/hatch/variants/... PS2, Line 46: #ifdef DPTF_ENABLE_CHARGER
Can we get rid of this? Its defined just above here.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31276 )
Change subject: mb/google/hatch: Enable DPTF functionality ......................................................................
mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/devicetree.cb A src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl 4 files changed, 101 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 93f7fc0..e6321ba 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -59,4 +59,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..aaef663 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..6e818f6 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl>
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Furquan Shaikh (Code Review) -
Patrick Georgi (Code Review)
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Sumeet R Pawnikar (Code Review)