[S] Change in coreboot[master]: mb/msi/ms7d25: Disable PCIe hotplug

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69822 )

Change subject: mb/msi/ms7d25: Disable PCIe hotplug
......................................................................

mb/msi/ms7d25: Disable PCIe hotplug

The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.

Signed-off-by: Michał Żygowski 
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
---
M src/mainboard/msi/ms7d25/devicetree.cb
1 file changed, 21 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Singer: Looks good to me, approved

diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index e175afa..91b55bb 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -98,7 +98,7 @@
    		register "cpu_pcie_rp[CPU_RP(2)]" = "{
    			.clk_src = 0,
    			.clk_req = 0,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
    			.PcieRpL1Substates = L1_SS_L1_2,
    			.pcie_rp_aspm = ASPM_L0S_L1,
    		}"
@@ -141,7 +141,7 @@
    		register "pch_pcie_rp[PCH_RP(1)]" = "{
    			.clk_src = 10,
    			.clk_req = 10,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
    			.PcieRpL1Substates = L1_SS_L1_2,
    			.pcie_rp_aspm = ASPM_L0S_L1,
    		}"
@@ -152,7 +152,7 @@
    		register "pch_pcie_rp[PCH_RP(2)]" = "{
    			.clk_src = 17,
    			.clk_req = 17,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
    			.PcieRpL1Substates = L1_SS_L1_2,
    			.pcie_rp_aspm = ASPM_L0S_L1,
    		}"
@@ -174,7 +174,7 @@
    		register "pch_pcie_rp[PCH_RP(5)]" = "{
    			.clk_src = 15,
    			.clk_req = 15,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
    			.PcieRpL1Substates = L1_SS_L1_2,
    			.pcie_rp_aspm = ASPM_L0S_L1,
    		}"