Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
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Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/27972/5/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/5/src/arch/riscv/misaligend.c@242
PS5, Line 242:                          * memory access */
code indent should use tabs where possible

https://review.coreboot.org/#/c/27972/5/src/arch/riscv/trap_handler.c
File src/arch/riscv/trap_handler.c:

https://review.coreboot.org/#/c/27972/5/src/arch/riscv/trap_handler.c@191
PS5, Line 191: 	write_csr(sepc, read_csr(mepc));
'sepc' may be misspelled - perhaps 'spec'?