[M] Change in coreboot[main]: soc/common/smbus: Support reading SPD5 hubs for DDR5

[Matt DeVillier (Code Review)]

Attention is currently required from: Angel Pons, Balaji Manigandan, Balaji Manigandan, Eric Lai, Haribalaraman Ramasubramanian, Jeremy Soller, Kapil Porwal, Karthik Ramasubramanian, Kyösti Mälkki, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Paul Menzel, Raj Astekar, Reka Norman, Rizwan Qureshi, Subrata Banik, Subrata Banik, Tarun Tuli, Tim Crawford, Tim Wawrzynczak.

Matt DeVillier has posted comments on this change by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email )

Change subject: soc/common/smbus: Support reading SPD5 hubs for DDR5
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Patch Set 16:

(1 comment)

File src/soc/intel/common/block/smbus/smbuslib.c:

https://review.coreboot.org/c/coreboot/+/52731/comment/38f37cb5_1e89665f?usp... :
PS14, Line 117: 	if (is_spd5_hub(addr)) {
> If we could make the platforms select USE_DDRx in their Kconfigs, then the compiler should optimize out these unused code paths.
>
> Or at least have the SoC's/northbridges select USE_DDRx the hardware can support. E.g. alderlake could select USE_DDR5 and USE_DDR4. Older SoCs/northbridges may select DDR3 only.

+1