Change in ...coreboot[master]: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode - coreboot-gerrit

7 Feb 2019


      Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )
Change subject: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
......................................................................
Patch Set 3:
is the default PCI mode? (since you're not explicitly setting it)
what are the consequences of not passing the correct mode to FSP?
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/29284
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8
Gerrit-Change-Number: 29284
Gerrit-PatchSet: 3
Gerrit-Owner: Frans Hendriks fhendriks@eltan.com
Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org
Gerrit-Reviewer: Frans Hendriks fhendriks@eltan.com
Gerrit-Reviewer: Hannah Williams hannah.williams@intel.com
Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Matt DeVillier matt.devillier@gmail.com
Gerrit-Comment-Date: Thu, 07 Feb 2019 05:20:48 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment