Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62919 )

Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
......................................................................

soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config

This change provides config for devicetree to control ASPM per port

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.

Signed-off-by: Kevin Chang 
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang 
Reviewed-by: Eric Lai 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Martin L Roth 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 34 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Peichao Wang: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 2f3027d..4a27cb5 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -297,6 +297,26 @@
    return ctl - 1;
 }

+/*
+ * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
+ * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
+ * that the mainboard setting does not disable ASPM incorrectly, chip
+ * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
+ * get_aspm_control() ensures that the right UPD value is set in fsp_params.
+ * 0: Use FSP UPD default
+ * 1: Disable ASPM
+ * 2: L0s only
+ * 3: L1 only
+ * 4: L0s and L1
+ * 5: Auto configuration
+ */
+static unsigned int get_aspm_control(enum ASPM_control ctl)
+{
+	if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT))
+		ctl = ASPM_AUTO;
+	return ctl - 1;
+}
+
 /* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */
 static uint16_t get_vccin_aux_imon_iccmax(void)
 {
@@ -632,6 +652,8 @@
    	s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
    	s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
    	s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		if (rp_cfg->pcie_rp_aspm)
+			s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
    }
 }

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 2f3b83c..66ced7e 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -42,6 +42,16 @@
    L1_SS_L1_2,
 };

+/* This enum is for passing into an FSP UPD, typically ASPM */
+enum ASPM_control {
+	ASPM_DEFAULT,
+	ASPM_DISABLE,
+	ASPM_L0S,
+	ASPM_L1,
+	ASPM_L0S_L1,
+	ASPM_AUTO,
+};
+
 /* PCIe Root Ports */
 struct pcie_rp_config {
    /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
@@ -51,6 +61,8 @@
    enum pcie_rp_flags flags;
    /* PCIe RP L1 substate */
    enum L1_substates_control PcieRpL1Substates;
+	/* PCIe RP ASPM */
+	enum ASPM_control pcie_rp_aspm;
 };

/*