Change in coreboot[master]: soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax

[Felix Singer (Code Review)]

Attention is currently required from: Patrick Rudolph.
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60664 )

Change subject: soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
......................................................................

soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax

Replace `LEqual(a, b)` with `a == b`.

Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc
Signed-off-by: Felix Singer 
---
M src/soc/intel/cannonlake/acpi/pch_hda.asl
M src/soc/intel/cannonlake/acpi/scs.asl
2 files changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/60664/1

diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl
index db2d664..85182f9 100644
--- a/src/soc/intel/cannonlake/acpi/pch_hda.asl
+++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl
@@ -26,17 +26,17 @@
     */
    Method (_DSM, 4)
    {
-		If (LEqual (Arg0, ^UUID)) {
+		If (Arg0 == ^UUID) {
    		/*
    		 * Function 0: Function Support Query
    		 * Returns a bitmask of functions supported.
    		 */
-			If (LEqual (Arg2, Zero)) {
+			If (Arg2 == 0) {
    			/*
    			 * NHLT Query only supported for revision 1 and
    			 * if NHLT address and length are set in NVS.
    			 */
-				If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) {
+				If (Arg1 == 1 && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) {
    				Return (Buffer (One) { 0x03 })
    			} Else {
    				Return (Buffer (One) { 0x01 })
@@ -50,7 +50,7 @@
    		 *
    		 * Returns a pointer to NHLT table in memory.
    		 */
-			If (LEqual (Arg2, One)) {
+			If (Arg2 == 1) {
    			CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
    			CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
    			CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 462e65a..4c01b48 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -73,7 +73,7 @@
    	 */
    	Method (_DSM, 4)
    	{
-			If (LEqual (Arg0, ^DSUU)) {
+			If (Arg0 == ^DSUU) {
    			/* Check the revision */
    			If (LGreaterEqual (Arg1, Zero)) {
    				/*
@@ -92,8 +92,8 @@
    				 * Bit 6 - Indicates support for HS400 mode
    				 * Bit 9 - Indicates eMMC I/O Driver Strength
    				 */
-					If (LEqual (Arg2, Zero)) {
-						If (Lequal (VDID, 0x02c48086) ) {
+					If (Arg2 == 0) {
+						If (VDID == 0x02c48086) {
    						/*
    						 * Set bit 9 for CML eMMC to indicate
    						 * eMMC I/O driver strength is supported
@@ -111,7 +111,7 @@
    				 * 3 - 100 ohm
    				 * 4 - 40 ohm
    				 */
-					If (LEqual (Arg2, 9)) {
+					If (Arg2 == 9) {
    					Return(Buffer() {0x4})
    				}
    			}
@@ -146,7 +146,7 @@
    	 */
    	Method (_DSM, 4)
    	{
-			If (LEqual (Arg0, ^DSUU)) {
+			If (Arg0 == ^DSUU) {
    			/* Check the revision */
    			If (LGreaterEqual (Arg1, Zero)) {
    				/*
@@ -165,7 +165,7 @@
    				 * For SD we have to support functions to
    				 * set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
    				 */
-					If (LEqual (Arg2, Zero)) {
+					If (Arg2 == 0) {
    					Return (Buffer () { 0x19 })
    				}
    				/*
@@ -175,7 +175,7 @@
    				 * UHS SD card on PCH. This is to compensate
    				 * for the SD VR slowness.
    				 */
-					If (LEqual (Arg2, 3)) {
+					If (Arg2 == 3) {
    					Sleep (100)
    					Return(Buffer () { 0x00 })
    				}
@@ -186,7 +186,7 @@
    				 * UHS SD card on PCH. This is to compensate
    				 * for the SD VR slowness.
    				 */
-					If (LEqual (Arg2, 4)) {
+					If (Arg2 == 4) {
    					Sleep (100)
    					Return(Buffer () { 0x00 })
    				}