Change in coreboot[master]: soc/mediatek: Add PCIe support

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Shelley Chen, Hung-Te Lin, Furquan Shaikh, Yu-Ping Wu, Jianjun Wang.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 )

Change subject: soc/mediatek: Add PCIe support
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Patch Set 9:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/56791/comment/45a23d00_46b6176d 
PS9, Line 12:   - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
Is this publicly available? If not, (how) can one obtain it?

Patchset:

PS9: 
IMHO this patch does too much at once for review. PCIe is organized
in layers and this change seems to try to cover all at once. Some
parts are Mediatek specific, others are just PCI standard (like the
resource allocation). It would be nice to split at least all the
standard things into a separate patch (if there is anything left
that is not already covered by common coreboot code).

File src/soc/mediatek/common/Kconfig:

https://review.coreboot.org/c/coreboot/+/56791/comment/4c91d22b_abc07c5b 
PS9, Line 46: 	bool "Enable MediaTek PCIe support"
Should this have a prompt? I guess at least the board code should know
if there is PCIe and select it? If that's the case, you could enable
NO_ECAM_MMCONF_SUPPORT conditionally for the SOC_MEDIATEK_COMMON
config above:

config SOC_MEDIATEK_COMMON
            bool
            select NO_ECAM_MMCONF_SUPPORT if PCI

Then the SoC/board Kconfig would only have to select PCI.

File src/soc/mediatek/common/pcie.c:

https://review.coreboot.org/c/coreboot/+/56791/comment/a9f27a9e_65c1e408 
PS2, Line 329: mtk_pcie_gen3_probe
> > Sorry for the late response, the device_operations has been used by soc_ops, can we still add this […]

For the IO windows, you have to implement your own version of
pci_domain_read_resources(). Beside mtk_pcie_startup_port()
which looks vendor specific, these IO windows are the only
non-standard thing I've spotted.

Maybe setting the domain ops should be done per SoC, i.e.
in the follow-up change?