Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
nb/intel/gm45: Fix compilation on x86_64
Fix integer-pointer conversion to allow the code to be compiled under x86_64. This commit doesn't change any functionality.
Tested on Lenovo T500 with additional patches.
Change-Id: Ic8b1f99cb4a8c09237f4644a7438fba34597d65c Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/southbridge/intel/i82801jx/lpc.c 10 files changed, 23 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45824/1
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 95457fb..01a645f 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -231,9 +231,9 @@ * MCHBAR */
-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + x))
#define HPLLVCO_MCHBAR 0x0c0f
@@ -395,7 +395,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void); -u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); +uintptr_t raminit_get_rank_addr(unsigned int channel, unsigned int rank);
void raminit_rcomp_calibration(stepping_t stepping); void raminit_reset_readwrite_pointers(void); diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 09df12d..d7a54d8 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,7 +37,8 @@
/* setup somewhere */ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); + /* FIXME: Why is GTT cleared here and who sets up BAR0? */ + void *bar = (void *)(uintptr_t)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
/* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8c27d50..5df4f01 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -124,7 +124,7 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem;
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7fc97f01..4a9035b 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1575,8 +1575,8 @@ /* We won't do this in dual-interleaved mode, so don't care about the offset. Mirrored ranks aren't taken into account here. */ - const u32 rankaddr = raminit_get_rank_addr(ch, r); - printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); + const uintptr_t rankaddr = raminit_get_rank_addr(ch, r); + printk(BIOS_DEBUG, "JEDEC init @0x%08zx\n", rankaddr); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); read32((u32 *)(rankaddr | WL)); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3); @@ -1658,7 +1658,7 @@ } }
-u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank) +uintptr_t raminit_get_rank_addr(unsigned int channel, unsigned int rank) { if (!channel && !rank) return 0; /* Address of first rank */ @@ -1670,7 +1670,7 @@ rank = 3; /* Highest rank per channel */ channel--; } - const u32 reg = MCHBAR32(CxDRBy_MCHBAR(channel, rank)); + const uintptr_t reg = MCHBAR32(CxDRBy_MCHBAR(channel, rank)); /* Bound is in 32MB. */ return ((reg & CxDRBy_BOUND_MASK(rank)) >> CxDRBy_BOUND_SHIFT(rank)) << 25; } diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index e8d719f..31f6380 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -7,7 +7,7 @@ #include "gm45.h"
typedef struct { - u32 addr[RANKS_PER_CHANNEL]; + uintptr_t addr[RANKS_PER_CHANNEL]; unsigned int count; } address_bunch_t;
@@ -415,7 +415,7 @@ MCHBAR8(0x0218) |= 0x1 << 4;
for (i = 0; i < addresses->count; ++i) { - const unsigned int addr = addresses->addr[i]; + const uintptr_t addr = addresses->addr[i]; unsigned int off; for (off = 0; off < 640; off += 8) { const u32 pattern = write_training_schedule[off >> 3]; diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 1535452..9f60f87 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -161,7 +161,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) { - u32 address; + uintptr_t address; int rank, lane; u8 count, count1; u8 data[8]; @@ -357,7 +357,7 @@ { int i, rank, lane; volatile u8 data[8]; - u32 address; + uintptr_t address; u8 bytelane_error = 0;
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) { @@ -436,7 +436,8 @@ int do_read_training(struct sysinfo *s) { int loop, channel, i, lane, rank; - u32 address, content; + uintptr_t address; + u32 content; u8 dqs_lower[TOTAL_BYTELANES]; u8 dqs_upper[TOTAL_BYTELANES]; struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES]; @@ -626,7 +627,7 @@
static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, u8 high_found[8]) { - u32 address = test_address(channel, rank); + uintptr_t address = test_address(channel, rank); int samples, lane;
memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 5e46270..5218100 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -74,7 +74,7 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem;
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 617ce11..92d234a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1296,7 +1296,7 @@
void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { - u32 addr = test_address(ch, r); + uintptr_t addr = test_address(ch, r); u8 data8 = cmd; u32 data32;
@@ -2136,7 +2136,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12))); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 82481ab..c32ec54 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -23,7 +23,7 @@ asm volatile("mfence":::); }
-static u8 sampledqs(u32 addr, u8 lane, u8 channel) +static u8 sampledqs(uintptr_t addr, u8 lane, u8 channel) { u32 sample_offset = 0x400 * channel + 0x561 + lane * 4;
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2f7b516..5ddbaa0 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -495,7 +495,7 @@
/* Add it to SSDT. */ acpigen_write_scope("\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } }
Hello Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45824
to look at the new patch set (#2).
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
nb/intel/gm45: Fix compilation on x86_64
Fix integer-pointer conversion to allow the code to be compiled under x86_64. This commit doesn't change any functionality.
Tested on Lenovo T500 with additional patches.
Change-Id: Ic8b1f99cb4a8c09237f4644a7438fba34597d65c Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/southbridge/intel/i82801jx/lpc.c 10 files changed, 23 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45824/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/gm45.h:
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... PS2, Line 234: #define MCHBAR8(x) *((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + x)) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... PS2, Line 235: #define MCHBAR16(x) *((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + x)) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... PS2, Line 236: #define MCHBAR32(x) *((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + x)) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/x4x/r... File src/northbridge/intel/x4x/raminit_ddr23.c:
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/x4x/r... PS2, Line 2139: read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12))); line over 96 characters
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45824/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45824/2//COMMIT_MSG@7 PS2, Line 7: gm45 x4x is also affected by this patch. Is either of them build-tested?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Patch Set 2: Code-Review+1
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/iommu.c:
https://review.coreboot.org/c/coreboot/+/45824/2/src/northbridge/intel/gm45/... PS2, Line 40: / This actually dead code. See https://review.coreboot.org/c/coreboot/+/17645
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45824
to look at the new patch set (#3).
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
nb/intel/gm45: Fix compilation on x86_64
Fix integer-pointer conversion to allow the code to be compiled under x86_64. This commit doesn't change any functionality.
Tested on Lenovo T500 with additional patches.
Change-Id: Ic8b1f99cb4a8c09237f4644a7438fba34597d65c Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c 8 files changed, 17 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45824/3
Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45824 )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Patch Set 3: Code-Review+2
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45824?usp=email )
Change subject: nb/intel/gm45: Fix compilation on x86_64 ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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build bot (Jenkins) (Code Review)
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Martin L Roth (Code Review)
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Patrick Rudolph (Code Review)