[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Chris Wang, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Dtrain Hsu, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73124

to look at the new patch set (#6).

Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter
......................................................................

soc/amd/mendocino: Remove the SPL DPTC parameter

The SPL parameter for DPTC settings is not available for STT-enabled
platforms. It needs to be removed to avoid confusing STT calculations.

BUG=b:265267957
BRANCH=none
TEST=Run the WebGL aquarium with 5000 fish and verify that
there are no power drop peaks.

Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a
Signed-off-by: Chris Wang 
---
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
M src/mainboard/google/skyrim/variants/whiterun/overridetree.cb
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/root_complex.c
6 files changed, 22 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/73124/6