Change in coreboot[master]: mb/google/brya/var/taeko: Enable CPU PCIE RP 1

[Joey Peng (Code Review)]

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59080 )

Change subject: mb/google/brya/var/taeko: Enable CPU PCIE RP 1
......................................................................

mb/google/brya/var/taeko: Enable CPU PCIE RP 1

Modify settings to enable CPU PCIE RP 1 according to schematics.

BUG=b:205504257
TEST=emerge-brya coreboot and can successfully boot with ssd and emmc.

Signed-off-by: Joey Peng 
Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6
---
M src/mainboard/google/brya/variants/taeko/gpio.c
M src/mainboard/google/brya/variants/taeko/overridetree.cb
2 files changed, 31 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/59080/1

diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c
index b67cc49..7ef9868 100644
--- a/src/mainboard/google/brya/variants/taeko/gpio.c
+++ b/src/mainboard/google/brya/variants/taeko/gpio.c
@@ -47,8 +47,8 @@

/* D3  : ISH_GP3 ==> NC */
    PAD_NC(GPP_D3, NONE),
-	/* D5  : SRCCLKREQ0# ==> NC */
-	PAD_NC(GPP_D5, NONE),
+	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
    /* D9  : ISH_SPI_CS# ==> NC */
    PAD_NC(GPP_D9, NONE),
    /* D10 : ISH_SPI_CLK ==> NC */
@@ -175,6 +175,28 @@
     * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
     */
    PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+
 };

const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 8ad5479..d6d7c9b 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -221,6 +221,13 @@
    			device generic 0 alias dptf_policy on end
    		end
    	end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+			}"
+		end
    	device ref tbt_pcie_rp0 off end
    	device ref tbt_pcie_rp1 off end
    	device ref tbt_pcie_rp2 off end