Change in ...coreboot[master]: soc/intel/cannonlake/romstage/fsp_params.c: use pcidev_path_on_root

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30793

Change subject: soc/intel/cannonlake/romstage/fsp_params.c: use pcidev_path_on_root
......................................................................

soc/intel/cannonlake/romstage/fsp_params.c: use pcidev_path_on_root

Change-Id: I77e924f8c2e394d1087801f83f002c8a7b0fe504
Signed-off-by: Angel Pons 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 13 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30793/1

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 91810e8..5ec4d88 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -25,7 +25,7 @@
 {
    unsigned int i;
    uint32_t mask = 0;
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	const struct device *dev;

/* Set IGD stolen size to 64MB. */
    m_cfg->IgdDvmt50PreAlloc = 2;
@@ -46,29 +46,27 @@
    m_cfg->PrmrrSize = config->PrmrrSize;
    m_cfg->EnableC6Dram = config->enable_c6dram;
    m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+	m_cfg->VmxEnable = config->VmxEnable;
+	m_cfg->PchIshEnable = 0;
+	m_cfg->PchHdaEnable = 0;
+	m_cfg->SaIpuEnable = 0;
    /* Disable Vmx if Vt-d is already disabled */
    if (config->VtdDisable)
    	m_cfg->VmxEnable = 0;
-	else
-		m_cfg->VmxEnable = config->VmxEnable;
 #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
    m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
 #endif
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
    /* If ISH is enabled, enable ISH elements */
-	if (!dev)
-		m_cfg->PchIshEnable = 0;
-	else
+	if (dev)
    	m_cfg->PchIshEnable = dev->enabled;

/* If HDA is enabled, enable HDA elements */
-	dev = dev_find_slot(0, PCH_DEVFN_HDA);
-	if (!dev)
-		m_cfg->PchHdaEnable = 0;
-	else
+	dev = pcidev_path_root(PCH_DEVFN_HDA);
+	if (dev)
    	m_cfg->PchHdaEnable = dev->enabled;

/* Enable IPU only if the device is enabled */
-	m_cfg->SaIpuEnable = 0;
    dev = pcidev_path_on_root(SA_DEVFN_IPU);
    if (dev)
    	m_cfg->SaIpuEnable = dev->enabled;
@@ -76,8 +74,8 @@

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
-	const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
    assert(dev != NULL);
    const config_t *config = dev->chip_info;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -85,9 +83,8 @@
    soc_memory_init_params(m_cfg, config);

/* Enable SMBus controller based on config */
-	if (!smbus)
-		m_cfg->SmbusEnable = 0;
-	else
+	m_cfg->SmbusEnable = 0;
+	if (smbus)
    	m_cfg->SmbusEnable = smbus->enabled;
    /* Set debug probe type */
    m_cfg->PlatformDebugConsent = config->DebugConsent;

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30793 )

Change subject: soc/intel/cannonlake/romstage/fsp_params.c: use pcidev_path_on_root
......................................................................

Abandoned