Change in coreboot[master]: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40848 )
Change subject: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c 2 files changed, 11 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40848/1
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index da97535..6ca4e64 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -58,7 +58,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -68,9 +68,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b406096..3f83e08 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -328,9 +328,9 @@ * that requires setting up the 64-bit BAR. */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_COMMAND, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); }
@@ -452,7 +452,7 @@ /* Common PCI device function disable. */ void southcluster_enable_dev(struct device *dev) { - uint32_t reg32; + uint16_t reg16;
if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -461,10 +461,10 @@ dev_path(dev), slot, func);
/* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16);
/* Place device in D3Hot */ if (place_device_in_d3hot(dev) < 0) { @@ -477,9 +477,7 @@ sc_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } }
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40848 )
Change subject: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40848 )
Change subject: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register ......................................................................
soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c 2 files changed, 11 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index da97535..6ca4e64 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -58,7 +58,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -68,9 +68,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b406096..3f83e08 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -328,9 +328,9 @@ * that requires setting up the 64-bit BAR. */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_COMMAND, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); }
@@ -452,7 +452,7 @@ /* Common PCI device function disable. */ void southcluster_enable_dev(struct device *dev) { - uint32_t reg32; + uint16_t reg16;
if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -461,10 +461,10 @@ dev_path(dev), slot, func);
/* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16);
/* Place device in D3Hot */ if (place_device_in_d3hot(dev) < 0) { @@ -477,9 +477,7 @@ sc_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } }
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40848 )
Change subject: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 3:
a
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)