Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48252 )
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has reached EVT exit parity.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 48 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/48252/1
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 57e727f..a3d34eb 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -9,23 +9,25 @@ OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
-Delta Lake server is a single socket Cooper Lake Scalable Processor server. +Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled.
-The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners +The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative -solution. This development is moving toward EVT exit equivalent status. +solution. This development reached EVT exit equivalent status.
## Required blobs
This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP - (Mass Production) of CooperLake Scalable Processor when the FSP is mature. + (Mass Production) of CPX-SP. - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. -- ME binary: Not yet available to the public. +- ME binary: Ignition binary will be made public some time after the MP + of CPX-SP. +- ACM binaries: only required for CBnT enablement.
## Payload - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. @@ -48,6 +50,16 @@ To connect to console through SOL (Serial Over Lan): sol-util slotx
+## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. + ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs. @@ -61,8 +73,12 @@ - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String + - Type 16 -- Physical Memory Array + - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 32 -- System Boot Information - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information - Type 127 -- End-of-Table - BMC integration: - BMC readiness check @@ -71,6 +87,12 @@ - POST complete pin acknowledgement - Check BMC version: ipmidump -device - SEL record generation +- Converged Bootguard and TXT (CBnT) + - TPM + - Bootguard profile 0T + - TXT + - SRTM (verified through tboot) + - memory secret clearance upon ungraceful shutdown - Early serial output - port 80h direct to GPIO - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT @@ -87,44 +109,40 @@ - Power button - localboot - netboot from IPv6 -- TPM +- basic memory hardware error injection/detection (SMI handler not upstreamed) +- basic PCIe hardware error injection/detection (SMI handler not upstreamed)
## Stress/performance tests passed -- OS warm reboot (300 cycles) -- DC reboot (300 cycles) -- AC reboot (300 cycle) +- OS warm reboot (1000 cycles) +- DC reboot (1000 cycles) +- AC reboot (1000 cycle) - Mprime test (6 hours) - StressAppTest (6 hours) + +## Performance tests on par with traditional firmware - Ptugen (6 hours) -- MLC (Intel Memory Latency Check) - Linkpack - Iperf(IPv6) - FIO
-## Firmware configurations -[ChromeOS VPD] is used to store most of the firmware configurations. -RO_VPD region holds default values, while RW_VPD region holds customized -values. - -VPD variables supported are: -- firmware_version: This variable holds overall firmware version. coreboot - uses that value to populate smbios type 1 version field. -- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. +## Other tests passed +- Power +- Thermal
## Known issues -- spsInfoLinux64 command fail to return ME version. -- fwts test failures related to mtrr. -- kernel error message related to SleepButton ACPI event. +- MLC (Intel Memory Latency Check) and stream performance issue +- PCH prochot assertion during FSP-S execution +- HECI access at OS run time: + - spsInfoLinux64 command fail to return ME version + - ptugen command fail to get memory power
## Feature gaps -- SMBIOS: - - Type 16 -- Physical Memory Array - - Type 17 -- Memory Device - - Type 19 -- Memory Array Mapped Address - - Type 41 -- Onboard Devices Extended Information -- Verified measurement through CBnT -- Boot guard of CBnT -- RO_VPD region as well as other RO regions are not write protected. +- flashrom command not able to update ME region +- ACPI APEI tables +- PCIe hotplug, Virtual Pin Ports +- PCIe Live Error Recovery +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core
## Technology
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48252 )
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48252/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/48252/1/Documentation/mainboard/ocp... PS1, Line 134: - PCH prochot assertion during FSP-S execution PCH prochot is resolved with CB:47229, GPP_B20 boot complete pin shouldn't be pulled low too early.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48252 )
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48252/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/48252/1/Documentation/mainboard/ocp... PS1, Line 134: - PCH prochot assertion during FSP-S execution
PCH prochot is resolved with CB:47229, GPP_B20 boot complete pin shouldn't be pulled low too early.
Done
Hello build bot (Jenkins), Marc Jones, John Looney, Johnny Lin, insomniac, Stefan Reinauer, David Hendricks, Rocky Phagura, Arthur Heymans, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48252
to look at the new patch set (#2).
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has reached EVT exit parity. Update the documentation accordingly.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 49 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/48252/2
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48252 )
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Patch Set 2: Code-Review+2
Very nice work - and thanks for the detailed description!
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48252 )
Change subject: Documentation/mainboard/ocp: Update DeltaLake ......................................................................
Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has reached EVT exit parity. Update the documentation accordingly.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Christian Walter christian.walter@9elements.com --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 49 insertions(+), 30 deletions(-)
Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 57e727f..9ef2357 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -9,23 +9,25 @@ OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
-Delta Lake server is a single socket Cooper Lake Scalable Processor server. +Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled.
-The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners +The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative -solution. This development is moving toward EVT exit equivalent status. +solution. This development reached EVT exit equivalent status.
## Required blobs
This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP - (Mass Production) of CooperLake Scalable Processor when the FSP is mature. + (Mass Production) of CPX-SP. - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. -- ME binary: Not yet available to the public. +- ME binary: Ignition binary will be made public some time after the MP + of CPX-SP. +- ACM binaries: only required for CBnT enablement.
## Payload - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. @@ -48,6 +50,16 @@ To connect to console through SOL (Serial Over Lan): sol-util slotx
+## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. + ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs. @@ -61,8 +73,12 @@ - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String + - Type 16 -- Physical Memory Array + - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 32 -- System Boot Information - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information - Type 127 -- End-of-Table - BMC integration: - BMC readiness check @@ -71,6 +87,12 @@ - POST complete pin acknowledgement - Check BMC version: ipmidump -device - SEL record generation +- Converged Bootguard and TXT (CBnT) + - TPM + - Bootguard profile 0T + - TXT + - SRTM (verified through tboot) + - memory secret clearance upon ungraceful shutdown - Early serial output - port 80h direct to GPIO - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT @@ -87,44 +109,41 @@ - Power button - localboot - netboot from IPv6 -- TPM +- basic memory hardware error injection/detection (SMI handler not upstreamed) +- basic PCIe hardware error injection/detection (SMI handler not upstreamed)
## Stress/performance tests passed -- OS warm reboot (300 cycles) -- DC reboot (300 cycles) -- AC reboot (300 cycle) +- OS warm reboot (1000 cycles) +- DC reboot (1000 cycles) +- AC reboot (1000 cycle) - Mprime test (6 hours) - StressAppTest (6 hours) - Ptugen (6 hours) -- MLC (Intel Memory Latency Check) + +## Performance tests on par with traditional firmware +- coremark +- SpecCPU - Linkpack - Iperf(IPv6) - FIO
-## Firmware configurations -[ChromeOS VPD] is used to store most of the firmware configurations. -RO_VPD region holds default values, while RW_VPD region holds customized -values. - -VPD variables supported are: -- firmware_version: This variable holds overall firmware version. coreboot - uses that value to populate smbios type 1 version field. -- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. +## Other tests passed +- Power +- Thermal
## Known issues -- spsInfoLinux64 command fail to return ME version. -- fwts test failures related to mtrr. -- kernel error message related to SleepButton ACPI event. +- MLC (Intel Memory Latency Check) and stream performance issue +- HECI access at OS run time: + - spsInfoLinux64 command fail to return ME version + - ptugen command fail to get memory power
## Feature gaps -- SMBIOS: - - Type 16 -- Physical Memory Array - - Type 17 -- Memory Device - - Type 19 -- Memory Array Mapped Address - - Type 41 -- Onboard Devices Extended Information -- Verified measurement through CBnT -- Boot guard of CBnT -- RO_VPD region as well as other RO regions are not write protected. +- flashrom command not able to update ME region +- ACPI APEI tables +- PCIe hotplug, Virtual Pin Ports +- PCIe Live Error Recovery +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core
## Technology
-
Christian Walter (Code Review) -
Johnny Lin (Code Review)
-
Jonathan Zhang (Code Review)
-
Patrick Georgi (Code Review)