Change in coreboot[master]: md/intel/cedarisland_crb: use common driver to configure GPIO

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

md/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with AMI firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/1

diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c
index ea82ecc..752a9bf 100644
--- a/src/mainboard/intel/cedarisland_crb/bootblock.c
+++ b/src/mainboard/intel/cedarisland_crb/bootblock.c
@@ -10,9 +10,13 @@
 #include <soc/pcr_ids.h>
 #include <superio/aspeed/ast2400/ast2400.h>
 #include <superio/aspeed/common/aspeed.h>
+#include "include/gpio.h"

void bootblock_mainboard_early_init(void)
 {
+	/* pre-configure Lewisburg PCH GPIO pads */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
    /* Enable COM1 only */
    pcr_write32(PID_DMI, 0x2770, 0);
    pcr_write32(PID_DMI, 0x2774, 1);
diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h
new file mode 100644
index 0000000..6aca58d
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h
@@ -0,0 +1,543 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef CFG_PCH_GPIO_H
+#define CFG_PCH_GPIO_H
+
+#include <soc/gpio.h>
+
+/* GPIO configuration table for C627 Lewisburg PCH */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+	/* ------- GPIO Group GPP_A ------- */
+	/* GPP_A0 - ESPI_ALERT1# */
+	_PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010),
+	/* GPP_A1 - ESPI_IO0 */
+	_PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010),
+	/* GPP_A2 - ESPI_IO1 */
+	_PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010),
+	/* GPP_A3 - ESPI_IO2 */
+	_PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010),
+	/* GPP_A4 - ESPI_IO3 */
+	_PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010),
+	/* GPP_A5 - ESPI_CS0# */
+	_PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010),
+	/* GPP_A6 - ESPI_CS1# */
+	_PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010),
+	/* GPP_A7 - ESPI_ALERT0# */
+	_PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010),
+	/* GPP_A8 - CLKRUN# */
+	_PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010),
+	/* GPP_A9 - ESPI_CLK */
+	_PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010),
+	/* GPP_A10 - CLKOUT_LPC1 */
+	_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010),
+	/* GPP_A11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010),
+	/* GPP_A12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000),
+	/* GPP_A13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010),
+	/* GPP_A14 - ESPI_RESET# */
+	_PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010),
+	/* GPP_A15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010),
+	/* GPP_A16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010),
+	/* GPP_A17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000),
+	/* GPP_A18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000),
+	/* GPP_A19 - RESERVED */
+	/* GPP_A20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000),
+	/* GPP_A21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000),
+	/* GPP_A22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000),
+	/* GPP_A23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000),
+
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_B0 - CORE_VID0 */
+	_PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000),
+	/* GPP_B1 - CORE_VID1 */
+	_PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000),
+	/* GPP_B2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000),
+	/* GPP_B3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000),
+	/* GPP_B4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000),
+	/* GPP_B5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000),
+	/* GPP_B6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000),
+	/* GPP_B7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000),
+	/* GPP_B8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000),
+	/* GPP_B9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000),
+	/* GPP_B10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000),
+	/* GPP_B11 - RESERVED */
+	/* GPP_B12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000),
+	/* GPP_B13 - PLTRST# */
+	_PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000),
+	/* GPP_B14 - SPKR */
+	_PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000),
+	/* GPP_B15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000),
+	/* GPP_B16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000),
+	/* GPP_B17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000),
+	/* GPP_B18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000),
+	/* GPP_B19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000),
+	/* GPP_B20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000),
+	/* GPP_B21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000),
+	/* GPP_B22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000),
+	/* GPP_B23 - PCHHOT# */
+	_PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000),
+
+	/* ------- GPIO Group GPP_F ------- */
+	/* GPP_F0 - SATAXPCIE3 */
+	_PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000),
+	/* GPP_F1 - SATAXPCIE4 */
+	_PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000),
+	/* GPP_F2 - SATAXPCIE5 */
+	_PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000),
+	/* GPP_F3 - SATAXPCIE6 */
+	_PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000),
+	/* GPP_F4 - SATAXPCIE7 */
+	_PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000),
+	/* GPP_F5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000),
+	/* GPP_F6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000),
+	/* GPP_F7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000),
+	/* GPP_F8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000),
+	/* GPP_F9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000),
+	/* GPP_F10 - SATA_SCLOCK */
+	_PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000),
+	/* GPP_F11 - SATA_SLOAD */
+	_PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000),
+	/* GPP_F12 - SATA_SDATAOUT1 */
+	_PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000),
+	/* GPP_F13 - SATA_SDATAOUT2 */
+	_PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000),
+	/* GPP_F14 - SSATA_LED# */
+	_PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000),
+	/* GPP_F15 - USB_OC4# */
+	_PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000),
+	/* GPP_F16 - USB_OC5# */
+	_PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000),
+	/* GPP_F17 - USB_OC6# */
+	_PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000),
+	/* GPP_F18 - USB_OC7# */
+	_PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000),
+	/* GPP_F19 - LAN_SMBCLK */
+	_PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000),
+	/* GPP_F20 - LAN_SMBDATA */
+	_PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000),
+	/* GPP_F21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000),
+	/* GPP_F22 - SSATA_SCLOCK */
+	_PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000),
+	/* GPP_F23 - SSATA_SLOAD */
+	_PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000),
+
+	/* ------- GPIO Community 1 ------- */
+	/* ------- GPIO Group GPP_C ------- */
+	/* GPP_C0 - RESERVED */
+	/* GPP_C1 - RESERVED */
+	/* GPP_C2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000),
+	/* GPP_C3 - RESERVED */
+	/* GPP_C4 - RESERVED */
+	/* GPP_C5 - SML0ALERT# */
+	_PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	/* GPP_C8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000),
+	/* GPP_C9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010),
+	/* GPP_C10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000),
+	/* GPP_C11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000),
+	/* GPP_C12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000),
+	/* GPP_C13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000),
+	/* GPP_C14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000),
+	/* GPP_C15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000),
+	/* GPP_C16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000),
+	/* GPP_C17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000),
+	/* GPP_C18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000),
+	/* GPP_C19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000),
+	/* GPP_C20 - RESERVED */
+	/* GPP_C21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000),
+	/* GPP_C22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000),
+	/* GPP_C23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* GPP_D0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000),
+	/* GPP_D1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000),
+	/* GPP_D2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000),
+	/* GPP_D3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000),
+	/* GPP_D4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000),
+	/* GPP_D5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000),
+	/* GPP_D6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010),
+	/* GPP_D7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000),
+	/* GPP_D8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000),
+	/* GPP_D9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000),
+	/* GPP_D10 - SSATA_DEVSLP4 */
+	_PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000),
+	/* GPP_D11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000),
+	/* GPP_D12 - SSATA_SDATAOUT1 */
+	_PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000),
+	/* GPP_D13 - SML0BCLK_IE */
+	_PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000),
+	/* GPP_D14 - SML0BDATA_IE */
+	_PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000),
+	/* GPP_D15 - SSATA_SDATAOUT0 */
+	_PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000),
+	/* GPP_D16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000),
+	/* GPP_D17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000),
+	/* GPP_D18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000),
+	/* GPP_D19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000),
+	/* GPP_D20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000),
+	/* GPP_D21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000),
+	/* GPP_D22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000),
+	/* GPP_D23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_E ------- */
+	/* GPP_E0 - SATAXPCIE0 */
+	_PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000),
+	/* GPP_E1 - SATAXPCIE1 */
+	_PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000),
+	/* GPP_E2 - SATAXPCIE2 */
+	_PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000),
+	/* GPP_E3 - CPU_GP0 */
+	_PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000),
+	/* GPP_E4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000),
+	/* GPP_E5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000),
+	/* GPP_E6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000),
+	/* GPP_E7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000),
+	/* GPP_E8 - SATA_LED# */
+	_PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000),
+	/* GPP_E9 - USB_OC0# */
+	_PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000),
+	/* GPP_E10 - USB_OC1# */
+	_PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000),
+	/* GPP_E11 - USB_OC2# */
+	_PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000),
+	/* GPP_E12 - USB_OC3# */
+	_PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000),
+
+	/* ------- GPIO Community 2 ------- */
+	/* -------- GPIO Group GPD -------- */
+	/* GPD0 - RESERVED */
+	/* GPD1 - ACPRESENT */
+	_PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000),
+	/* GPD2 - GBE_WAKE# */
+	_PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000),
+	/* GPD3 - PWRBTN# */
+	_PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000),
+	/* GPD4 - SLP_S3# */
+	_PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000),
+	/* GPD5 - SLP_S4# */
+	_PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000),
+	/* GPD6 - SLP_A# */
+	_PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000),
+	/* GPD7 - GPIO */
+	_PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000),
+	/* GPD8 - GPIO */
+	_PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000),
+	/* GPD9 - GPIO */
+	_PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000),
+	/* GPD10 - SLP_S5# */
+	_PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000),
+	/* GPD11 - GBEPHY */
+	_PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000),
+
+	/* ------- GPIO Community 3 ------- */
+	/* ------- GPIO Group GPP_I ------- */
+	/* GPP_I0 - LAN_TDO */
+	_PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000),
+	/* GPP_I1 - LAN_TCK */
+	_PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000),
+	/* GPP_I2 - LAN_TMS */
+	_PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000),
+	/* GPP_I3 - LAN_TDI */
+	_PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000),
+	/* GPP_I4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000),
+	/* GPP_I5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000),
+	/* GPP_I6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000),
+	/* GPP_I7 - LAN_TRST_IN */
+	_PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000),
+	/* GPP_I8 - PCI_DIS */
+	_PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000),
+	/* GPP_I9 - LAN_DIS */
+	_PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000),
+	/* GPP_I10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Community 4 ------- */
+	/* ------- GPIO Group GPP_J ------- */
+	/* GPP_J0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000),
+	/* GPP_J1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000),
+	/* GPP_J2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000),
+	/* GPP_J3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000),
+	/* GPP_J4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000),
+	/* GPP_J5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000),
+	/* GPP_J6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000),
+	/* GPP_J7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000),
+	/* GPP_J8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000),
+	/* GPP_J9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000),
+	/* GPP_J10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000),
+	/* GPP_J11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000),
+	/* GPP_J12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000),
+	/* GPP_J13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000),
+	/* GPP_J14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000),
+	/* GPP_J15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000),
+	/* GPP_J16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000),
+	/* GPP_J17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000),
+	/* GPP_J18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000),
+	/* GPP_J19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000),
+	/* GPP_J20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000),
+	/* GPP_J21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000),
+	/* GPP_J22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000),
+	/* GPP_J23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_K ------- */
+	/* GPP_K0 - LAN_NCSI_CLK_IN */
+	_PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000),
+	/* GPP_K1 - LAN_NCSI_TXD0 */
+	_PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000),
+	/* GPP_K2 - LAN_NCSI_TXD1 */
+	_PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000),
+	/* GPP_K3 - LAN_NCSI_TX_EN */
+	_PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000),
+	/* GPP_K4 - LAN_NCSI_CRS_DV */
+	_PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000),
+	/* GPP_K5 - LAN_NCSI_RXD0 */
+	_PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000),
+	/* GPP_K6 - LAN_NCSI_RXD1 */
+	_PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000),
+	/* GPP_K7 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000),
+	/* GPP_K8 - LAN_NCSI_ARB_IN */
+	_PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000),
+	/* GPP_K9 - LAN_NCSI_ARB_OUT */
+	_PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000),
+	/* GPP_K10 - PE_RST# */
+	_PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000),
+
+	/* ------- GPIO Community 5 ------- */
+	/* ------- GPIO Group GPP_G ------- */
+	/* GPP_G0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000),
+	/* GPP_G1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000),
+	/* GPP_G2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000),
+	/* GPP_G3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000),
+	/* GPP_G4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000),
+	/* GPP_G5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000),
+	/* GPP_G6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000),
+	/* GPP_G7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000),
+	/* GPP_G8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000),
+	/* GPP_G9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000),
+	/* GPP_G10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000),
+	/* GPP_G11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000),
+	/* GPP_G12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000),
+	/* GPP_G13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000),
+	/* GPP_G14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000),
+	/* GPP_G15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000),
+	/* GPP_G16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000),
+	/* GPP_G17 - ADR_COMPLETE */
+	_PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000),
+	/* GPP_G18 - NMI# */
+	_PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000),
+	/* GPP_G19 - SMI# */
+	_PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000),
+	/* GPP_G20 - RESERVED */
+	/* GPP_G21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000),
+	/* GPP_G22 - n/a */
+	_PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000),
+	/* GPP_G23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_H ------- */
+	/* GPP_H0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000),
+	/* GPP_H1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000),
+	/* GPP_H2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000),
+	/* GPP_H3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000),
+	/* GPP_H4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000),
+	/* GPP_H5 - RESERVED */
+	/* GPP_H6 - SRCCLKREQ12# */
+	_PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000),
+	/* GPP_H7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000),
+	/* GPP_H8 - SRCCLKREQ14# */
+	_PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000),
+	/* GPP_H9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000),
+	/* GPP_H10 - RESERVED */
+	/* GPP_H11 - RESERVED */
+	/* GPP_H12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000),
+	/* GPP_H13 - RESERVED */
+	/* GPP_H14 - RESERVED */
+	/* GPP_H15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000),
+	/* GPP_H16 - RESERVED */
+	/* GPP_H17 - RESERVED */
+	/* GPP_H18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000),
+	/* GPP_H19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000),
+	/* GPP_H20 - SSATAXPCIE2 */
+	_PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000),
+	/* GPP_H21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000),
+	/* GPP_H22 - SSATAXPCIE4 */
+	_PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000),
+	/* GPP_H23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_L ------- */
+	/* GPP_L0 - RESERVED */
+	/* GPP_L1 - CSME_INTR_OUT */
+	_PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000),
+	/* GPP_L2 - TESTCH0_D0 */
+	_PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000),
+	/* GPP_L3 - TESTCH0_D1 */
+	_PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000),
+	/* GPP_L4 - TESTCH0_D2 */
+	_PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000),
+	/* GPP_L5 - TESTCH0_D3 */
+	_PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000),
+	/* GPP_L6 - TESTCH0_D4 */
+	_PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000),
+	/* GPP_L7 - TESTCH0_D5 */
+	_PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000),
+	/* GPP_L8 - TESTCH0_D6 */
+	_PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000),
+	/* GPP_L9 - TESTCH0_D7 */
+	_PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000),
+	/* GPP_L10 - TESTCH0_CLK */
+	_PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000),
+	/* GPP_L11 - TESTCH1_D0 */
+	_PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000),
+	/* GPP_L12 - TESTCH1_D1 */
+	_PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000),
+	/* GPP_L13 - TESTCH1_D2 */
+	_PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000),
+	/* GPP_L14 - TESTCH1_D3 */
+	_PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000),
+	/* GPP_L15 - TESTCH1_D4 */
+	_PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000),
+	/* GPP_L16 - TESTCH1_D5 */
+	_PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000),
+	/* GPP_L17 - TESTCH1_D6 */
+	_PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000),
+	/* GPP_L18 - TESTCH1_D7 */
+	_PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000),
+	/* GPP_L19 - TESTCH1_CLK */
+	_PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000),
+};
+
+#endif /* CFG_PCH_GPIO_H */

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

md/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with AMI firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/2

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40734

to look at the new patch set (#4).

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

md/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with AMI firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/4

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 4:

lgtm but why not rebase this on master? it is not dependant on prev patch, is it?

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40734

to look at the new patch set (#5).

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

md/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/5

[Lance Zhao (Code Review)]

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 5: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40734/5/src/mainboard/intel/cedaris... 
File src/mainboard/intel/cedarisland_crb/bootblock.c:

https://review.coreboot.org/c/coreboot/+/40734/5/src/mainboard/intel/cedaris... 
PS5, Line 17: pre-configure
pre-configure here stand for?

[Maxim Polyakov (Code Review)]

Hello Lance Zhao, build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40734

to look at the new patch set (#6).

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

md/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/6

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40734/5/src/mainboard/intel/cedaris... 
File src/mainboard/intel/cedarisland_crb/bootblock.c:

https://review.coreboot.org/c/coreboot/+/40734/5/src/mainboard/intel/cedaris... 
PS5, Line 17: pre-configure
> pre-configure here stand for?

I removed "pre"

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: md/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40734/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40734/6//COMMIT_MSG@7 
PS6, Line 7: md
mb?

Change in coreboot[master]: mb/intel/cedarisland_crb: use common driver to configure GPIO

[Maxim Polyakov (Code Review)]

Hello Lance Zhao, build bot (Jenkins), Andrey Petrov,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40734

to look at the new patch set (#7).

Change subject: mb/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

mb/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40734/7

Change in coreboot[master]: mb/intel/cedarisland_crb: use common driver to configure GPIO

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: mb/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40734/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40734/6//COMMIT_MSG@7 
PS6, Line 7: md
> mb?

Done

Change in coreboot[master]: mb/intel/cedarisland_crb: use common driver to configure GPIO

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: mb/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

Patch Set 7: Code-Review+2

I tested this patch stack on top of CB:40921 and can confirm inteltool report correct values

Change in coreboot[master]: mb/intel/cedarisland_crb: use common driver to configure GPIO

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40734 )

Change subject: mb/intel/cedarisland_crb: use common driver to configure GPIO
......................................................................

mb/intel/cedarisland_crb: use common driver to configure GPIO

According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734
Tested-by: build bot (Jenkins) 
Reviewed-by: Andrey Petrov 
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/include/gpio.h
2 files changed, 547 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Andrey Petrov: Looks good to me, approved

diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c
index ea82ecc..3be0f8b 100644
--- a/src/mainboard/intel/cedarisland_crb/bootblock.c
+++ b/src/mainboard/intel/cedarisland_crb/bootblock.c
@@ -10,9 +10,13 @@
 #include <soc/pcr_ids.h>
 #include <superio/aspeed/ast2400/ast2400.h>
 #include <superio/aspeed/common/aspeed.h>
+#include "include/gpio.h"

void bootblock_mainboard_early_init(void)
 {
+	/* Configure Lewisburg PCH GPIOs */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
    /* Enable COM1 only */
    pcr_write32(PID_DMI, 0x2770, 0);
    pcr_write32(PID_DMI, 0x2774, 1);
diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h
new file mode 100644
index 0000000..6aca58d
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h
@@ -0,0 +1,543 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef CFG_PCH_GPIO_H
+#define CFG_PCH_GPIO_H
+
+#include <soc/gpio.h>
+
+/* GPIO configuration table for C627 Lewisburg PCH */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+	/* ------- GPIO Group GPP_A ------- */
+	/* GPP_A0 - ESPI_ALERT1# */
+	_PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010),
+	/* GPP_A1 - ESPI_IO0 */
+	_PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010),
+	/* GPP_A2 - ESPI_IO1 */
+	_PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010),
+	/* GPP_A3 - ESPI_IO2 */
+	_PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010),
+	/* GPP_A4 - ESPI_IO3 */
+	_PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010),
+	/* GPP_A5 - ESPI_CS0# */
+	_PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010),
+	/* GPP_A6 - ESPI_CS1# */
+	_PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010),
+	/* GPP_A7 - ESPI_ALERT0# */
+	_PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010),
+	/* GPP_A8 - CLKRUN# */
+	_PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010),
+	/* GPP_A9 - ESPI_CLK */
+	_PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010),
+	/* GPP_A10 - CLKOUT_LPC1 */
+	_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010),
+	/* GPP_A11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010),
+	/* GPP_A12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000),
+	/* GPP_A13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010),
+	/* GPP_A14 - ESPI_RESET# */
+	_PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010),
+	/* GPP_A15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010),
+	/* GPP_A16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010),
+	/* GPP_A17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000),
+	/* GPP_A18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000),
+	/* GPP_A19 - RESERVED */
+	/* GPP_A20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000),
+	/* GPP_A21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000),
+	/* GPP_A22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000),
+	/* GPP_A23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000),
+
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_B0 - CORE_VID0 */
+	_PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000),
+	/* GPP_B1 - CORE_VID1 */
+	_PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000),
+	/* GPP_B2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000),
+	/* GPP_B3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000),
+	/* GPP_B4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000),
+	/* GPP_B5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000),
+	/* GPP_B6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000),
+	/* GPP_B7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000),
+	/* GPP_B8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000),
+	/* GPP_B9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000),
+	/* GPP_B10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000),
+	/* GPP_B11 - RESERVED */
+	/* GPP_B12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000),
+	/* GPP_B13 - PLTRST# */
+	_PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000),
+	/* GPP_B14 - SPKR */
+	_PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000),
+	/* GPP_B15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000),
+	/* GPP_B16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000),
+	/* GPP_B17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000),
+	/* GPP_B18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000),
+	/* GPP_B19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000),
+	/* GPP_B20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000),
+	/* GPP_B21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000),
+	/* GPP_B22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000),
+	/* GPP_B23 - PCHHOT# */
+	_PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000),
+
+	/* ------- GPIO Group GPP_F ------- */
+	/* GPP_F0 - SATAXPCIE3 */
+	_PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000),
+	/* GPP_F1 - SATAXPCIE4 */
+	_PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000),
+	/* GPP_F2 - SATAXPCIE5 */
+	_PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000),
+	/* GPP_F3 - SATAXPCIE6 */
+	_PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000),
+	/* GPP_F4 - SATAXPCIE7 */
+	_PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000),
+	/* GPP_F5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000),
+	/* GPP_F6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000),
+	/* GPP_F7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000),
+	/* GPP_F8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000),
+	/* GPP_F9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000),
+	/* GPP_F10 - SATA_SCLOCK */
+	_PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000),
+	/* GPP_F11 - SATA_SLOAD */
+	_PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000),
+	/* GPP_F12 - SATA_SDATAOUT1 */
+	_PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000),
+	/* GPP_F13 - SATA_SDATAOUT2 */
+	_PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000),
+	/* GPP_F14 - SSATA_LED# */
+	_PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000),
+	/* GPP_F15 - USB_OC4# */
+	_PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000),
+	/* GPP_F16 - USB_OC5# */
+	_PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000),
+	/* GPP_F17 - USB_OC6# */
+	_PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000),
+	/* GPP_F18 - USB_OC7# */
+	_PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000),
+	/* GPP_F19 - LAN_SMBCLK */
+	_PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000),
+	/* GPP_F20 - LAN_SMBDATA */
+	_PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000),
+	/* GPP_F21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000),
+	/* GPP_F22 - SSATA_SCLOCK */
+	_PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000),
+	/* GPP_F23 - SSATA_SLOAD */
+	_PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000),
+
+	/* ------- GPIO Community 1 ------- */
+	/* ------- GPIO Group GPP_C ------- */
+	/* GPP_C0 - RESERVED */
+	/* GPP_C1 - RESERVED */
+	/* GPP_C2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000),
+	/* GPP_C3 - RESERVED */
+	/* GPP_C4 - RESERVED */
+	/* GPP_C5 - SML0ALERT# */
+	_PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	/* GPP_C8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000),
+	/* GPP_C9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010),
+	/* GPP_C10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000),
+	/* GPP_C11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000),
+	/* GPP_C12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000),
+	/* GPP_C13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000),
+	/* GPP_C14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000),
+	/* GPP_C15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000),
+	/* GPP_C16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000),
+	/* GPP_C17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000),
+	/* GPP_C18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000),
+	/* GPP_C19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000),
+	/* GPP_C20 - RESERVED */
+	/* GPP_C21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000),
+	/* GPP_C22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000),
+	/* GPP_C23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* GPP_D0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000),
+	/* GPP_D1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000),
+	/* GPP_D2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000),
+	/* GPP_D3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000),
+	/* GPP_D4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000),
+	/* GPP_D5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000),
+	/* GPP_D6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010),
+	/* GPP_D7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000),
+	/* GPP_D8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000),
+	/* GPP_D9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000),
+	/* GPP_D10 - SSATA_DEVSLP4 */
+	_PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000),
+	/* GPP_D11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000),
+	/* GPP_D12 - SSATA_SDATAOUT1 */
+	_PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000),
+	/* GPP_D13 - SML0BCLK_IE */
+	_PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000),
+	/* GPP_D14 - SML0BDATA_IE */
+	_PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000),
+	/* GPP_D15 - SSATA_SDATAOUT0 */
+	_PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000),
+	/* GPP_D16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000),
+	/* GPP_D17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000),
+	/* GPP_D18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000),
+	/* GPP_D19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000),
+	/* GPP_D20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000),
+	/* GPP_D21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000),
+	/* GPP_D22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000),
+	/* GPP_D23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_E ------- */
+	/* GPP_E0 - SATAXPCIE0 */
+	_PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000),
+	/* GPP_E1 - SATAXPCIE1 */
+	_PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000),
+	/* GPP_E2 - SATAXPCIE2 */
+	_PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000),
+	/* GPP_E3 - CPU_GP0 */
+	_PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000),
+	/* GPP_E4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000),
+	/* GPP_E5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000),
+	/* GPP_E6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000),
+	/* GPP_E7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000),
+	/* GPP_E8 - SATA_LED# */
+	_PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000),
+	/* GPP_E9 - USB_OC0# */
+	_PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000),
+	/* GPP_E10 - USB_OC1# */
+	_PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000),
+	/* GPP_E11 - USB_OC2# */
+	_PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000),
+	/* GPP_E12 - USB_OC3# */
+	_PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000),
+
+	/* ------- GPIO Community 2 ------- */
+	/* -------- GPIO Group GPD -------- */
+	/* GPD0 - RESERVED */
+	/* GPD1 - ACPRESENT */
+	_PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000),
+	/* GPD2 - GBE_WAKE# */
+	_PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000),
+	/* GPD3 - PWRBTN# */
+	_PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000),
+	/* GPD4 - SLP_S3# */
+	_PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000),
+	/* GPD5 - SLP_S4# */
+	_PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000),
+	/* GPD6 - SLP_A# */
+	_PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000),
+	/* GPD7 - GPIO */
+	_PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000),
+	/* GPD8 - GPIO */
+	_PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000),
+	/* GPD9 - GPIO */
+	_PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000),
+	/* GPD10 - SLP_S5# */
+	_PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000),
+	/* GPD11 - GBEPHY */
+	_PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000),
+
+	/* ------- GPIO Community 3 ------- */
+	/* ------- GPIO Group GPP_I ------- */
+	/* GPP_I0 - LAN_TDO */
+	_PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000),
+	/* GPP_I1 - LAN_TCK */
+	_PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000),
+	/* GPP_I2 - LAN_TMS */
+	_PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000),
+	/* GPP_I3 - LAN_TDI */
+	_PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000),
+	/* GPP_I4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000),
+	/* GPP_I5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000),
+	/* GPP_I6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000),
+	/* GPP_I7 - LAN_TRST_IN */
+	_PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000),
+	/* GPP_I8 - PCI_DIS */
+	_PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000),
+	/* GPP_I9 - LAN_DIS */
+	_PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000),
+	/* GPP_I10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Community 4 ------- */
+	/* ------- GPIO Group GPP_J ------- */
+	/* GPP_J0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000),
+	/* GPP_J1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000),
+	/* GPP_J2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000),
+	/* GPP_J3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000),
+	/* GPP_J4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000),
+	/* GPP_J5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000),
+	/* GPP_J6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000),
+	/* GPP_J7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000),
+	/* GPP_J8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000),
+	/* GPP_J9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000),
+	/* GPP_J10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000),
+	/* GPP_J11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000),
+	/* GPP_J12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000),
+	/* GPP_J13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000),
+	/* GPP_J14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000),
+	/* GPP_J15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000),
+	/* GPP_J16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000),
+	/* GPP_J17 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000),
+	/* GPP_J18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000),
+	/* GPP_J19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000),
+	/* GPP_J20 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000),
+	/* GPP_J21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000),
+	/* GPP_J22 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000),
+	/* GPP_J23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_K ------- */
+	/* GPP_K0 - LAN_NCSI_CLK_IN */
+	_PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000),
+	/* GPP_K1 - LAN_NCSI_TXD0 */
+	_PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000),
+	/* GPP_K2 - LAN_NCSI_TXD1 */
+	_PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000),
+	/* GPP_K3 - LAN_NCSI_TX_EN */
+	_PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000),
+	/* GPP_K4 - LAN_NCSI_CRS_DV */
+	_PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000),
+	/* GPP_K5 - LAN_NCSI_RXD0 */
+	_PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000),
+	/* GPP_K6 - LAN_NCSI_RXD1 */
+	_PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000),
+	/* GPP_K7 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000),
+	/* GPP_K8 - LAN_NCSI_ARB_IN */
+	_PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000),
+	/* GPP_K9 - LAN_NCSI_ARB_OUT */
+	_PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000),
+	/* GPP_K10 - PE_RST# */
+	_PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000),
+
+	/* ------- GPIO Community 5 ------- */
+	/* ------- GPIO Group GPP_G ------- */
+	/* GPP_G0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000),
+	/* GPP_G1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000),
+	/* GPP_G2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000),
+	/* GPP_G3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000),
+	/* GPP_G4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000),
+	/* GPP_G5 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000),
+	/* GPP_G6 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000),
+	/* GPP_G7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000),
+	/* GPP_G8 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000),
+	/* GPP_G9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000),
+	/* GPP_G10 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000),
+	/* GPP_G11 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000),
+	/* GPP_G12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000),
+	/* GPP_G13 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000),
+	/* GPP_G14 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000),
+	/* GPP_G15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000),
+	/* GPP_G16 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000),
+	/* GPP_G17 - ADR_COMPLETE */
+	_PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000),
+	/* GPP_G18 - NMI# */
+	_PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000),
+	/* GPP_G19 - SMI# */
+	_PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000),
+	/* GPP_G20 - RESERVED */
+	/* GPP_G21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000),
+	/* GPP_G22 - n/a */
+	_PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000),
+	/* GPP_G23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_H ------- */
+	/* GPP_H0 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000),
+	/* GPP_H1 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000),
+	/* GPP_H2 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000),
+	/* GPP_H3 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000),
+	/* GPP_H4 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000),
+	/* GPP_H5 - RESERVED */
+	/* GPP_H6 - SRCCLKREQ12# */
+	_PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000),
+	/* GPP_H7 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000),
+	/* GPP_H8 - SRCCLKREQ14# */
+	_PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000),
+	/* GPP_H9 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000),
+	/* GPP_H10 - RESERVED */
+	/* GPP_H11 - RESERVED */
+	/* GPP_H12 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000),
+	/* GPP_H13 - RESERVED */
+	/* GPP_H14 - RESERVED */
+	/* GPP_H15 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000),
+	/* GPP_H16 - RESERVED */
+	/* GPP_H17 - RESERVED */
+	/* GPP_H18 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000),
+	/* GPP_H19 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000),
+	/* GPP_H20 - SSATAXPCIE2 */
+	_PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000),
+	/* GPP_H21 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000),
+	/* GPP_H22 - SSATAXPCIE4 */
+	_PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000),
+	/* GPP_H23 - GPIO */
+	_PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000),
+
+	/* ------- GPIO Group GPP_L ------- */
+	/* GPP_L0 - RESERVED */
+	/* GPP_L1 - CSME_INTR_OUT */
+	_PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000),
+	/* GPP_L2 - TESTCH0_D0 */
+	_PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000),
+	/* GPP_L3 - TESTCH0_D1 */
+	_PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000),
+	/* GPP_L4 - TESTCH0_D2 */
+	_PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000),
+	/* GPP_L5 - TESTCH0_D3 */
+	_PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000),
+	/* GPP_L6 - TESTCH0_D4 */
+	_PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000),
+	/* GPP_L7 - TESTCH0_D5 */
+	_PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000),
+	/* GPP_L8 - TESTCH0_D6 */
+	_PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000),
+	/* GPP_L9 - TESTCH0_D7 */
+	_PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000),
+	/* GPP_L10 - TESTCH0_CLK */
+	_PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000),
+	/* GPP_L11 - TESTCH1_D0 */
+	_PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000),
+	/* GPP_L12 - TESTCH1_D1 */
+	_PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000),
+	/* GPP_L13 - TESTCH1_D2 */
+	_PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000),
+	/* GPP_L14 - TESTCH1_D3 */
+	_PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000),
+	/* GPP_L15 - TESTCH1_D4 */
+	_PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000),
+	/* GPP_L16 - TESTCH1_D5 */
+	_PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000),
+	/* GPP_L17 - TESTCH1_D6 */
+	_PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000),
+	/* GPP_L18 - TESTCH1_D7 */
+	_PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000),
+	/* GPP_L19 - TESTCH1_CLK */
+	_PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000),
+};
+
+#endif /* CFG_PCH_GPIO_H */