Change in ...coreboot[master]: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32295
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
With commit '4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)' FSP is now requested to switch off HDA PCI device if it is disabled in devicetree. Doing so results in a warm restart. Normally this event will be stored in CMOS RAM (if the descriptor is configured to do so) and therefore no further resets are requested by FSP on the next boots as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery and therefore the CMOS is not backed up. This leads to reset requests from FSP after PCI enumeration on every boot. To avoid this reset enable HDA in devicetree for these mainboards. Though we do not have any usage of HDA it should not be an issue that the HDA device is now enabled. The benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32295/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index f3e8a77..539c8d9 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -68,7 +68,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 42c474e..aa1e46a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -60,7 +60,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index b6839c1..28d6aeb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -56,7 +56,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index e6feb48..865f9f5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -57,7 +57,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 15be7ff..f914906 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -59,7 +59,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32295/1/src/mainboard/siemens/mc_apl1/varian... File src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb:
https://review.coreboot.org/#/c/32295/1/src/mainboard/siemens/mc_apl1/varian... PS1, Line 71: Can you please insert a space? ...for all boards
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32295/1/src/mainboard/siemens/mc_apl1/varian... File src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb:
https://review.coreboot.org/#/c/32295/1/src/mainboard/siemens/mc_apl1/varian... PS1, Line 71:
Can you please insert a space? ... […]
Ups, sorry. Will do.
Hello Mario Scheithauer, Uwe Poeche, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32295
to look at the new patch set (#2).
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
With commit '4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)' FSP is now requested to switch off HDA PCI device if it is disabled in devicetree. Doing so results in a warm restart. Normally this event will be stored in CMOS RAM (if the descriptor is configured to do so) and therefore no further resets are requested by FSP on the next boots as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery and therefore the CMOS is not backed up. This leads to reset requests from FSP after PCI enumeration on every boot. To avoid this reset enable HDA in devicetree for these mainboards. Though we do not have any usage of HDA it should not be an issue that the HDA device is now enabled. The benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32295/2
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 3: Code-Review+2
We probably would rather not have FSP do unconditional warm resets, but I don't know the background about that API design choice.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+2
We probably would rather not have FSP do unconditional warm resets, but I don't know the background about that API design choice.
It is not that FSP _do_ the warm reset, it is more that it requests it and coreboot performs the warm reset. See https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/fsp2_0/... line 58 In any case it is not wanted here.
Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
Patch Set 3: Code-Review+1
Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32295 )
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants ......................................................................
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
With commit '4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)' FSP is now requested to switch off HDA PCI device if it is disabled in devicetree. Doing so results in a warm restart. Normally this event will be stored in CMOS RAM (if the descriptor is configured to do so) and therefore no further resets are requested by FSP on the next boots as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery and therefore the CMOS is not backed up. This leads to reset requests from FSP after PCI enumeration on every boot. To avoid this reset enable HDA in devicetree for these mainboards. Though we do not have any usage of HDA it should not be an issue that the HDA device is now enabled. The benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221 Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Uwe Poeche uwe.poeche@siemens.com Reviewed-by: Mario Scheithauer mario.scheithauer@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Mario Scheithauer: Looks good to me, approved Uwe Poeche: Looks good to me, but someone else must approve
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index f3e8a77..55e6105 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -68,7 +68,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 42c474e..a627e3e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -60,7 +60,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index b6839c1..a03f383 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -56,7 +56,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index e6feb48..53a3394 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -57,7 +57,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 15be7ff..f1ed5d2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -59,7 +59,7 @@ device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM - device pci 0e.0 off end # - Audio + device pci 0e.0 on end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0
-
Kyösti Mälkki (Code Review) -
Mario Scheithauer (Code Review)
-
Uwe Poeche (Code Review)
-
Werner Zeh (Code Review)