[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )

Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table
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Patch Set 4:

(3 comments)

File src/include/acpi/acpi.h:

https://review.coreboot.org/c/coreboot/+/78164/comment/efc776dc_cb33fcb7 :
PS4, Line 456: CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC
> CONFIG(SOC_INTEL_SLP_S0_FREQ_TSC)

Acknowledged

https://review.coreboot.org/c/coreboot/+/78164/comment/4f13255a_cc0e1bde :
PS4, Line 461:
> another thought why not set the macro based on the CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC value? and defau […]

Acknowledged

File src/soc/intel/common/block/acpi/lpit.c:

https://review.coreboot.org/c/coreboot/+/78164/comment/357547b8_c9aed1fb :
PS3, Line 34: MSR value return in usec
> > MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we  […]

Ref. https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.... Sec 2.2.1: Residency counter frequency in cycles per second. A value of 0 indicates that counter runs at TSC frequency. Valid only if Residency Counter is present.
Ref. https://www.intel.com/content/dam/develop/external/us/en/documents/335592-sd... page 121, MSR 0x632 : package C10 residency counter, count at the same frequency as the TSC.
- hence pkg_counter->counter_frequency to be zero.
- In past this did not make any impact as ACPI_LPIT_CTR_FREQ_TSC was ZERO.

today:
 a) CPU PKG C10 - (#cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us) - no issue.
 b) Platform Controller Hub (PCH) SLP_S0  - (#cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us)  issue across all platform. this patch will fix the MTL;

NOTE: Let me submit the fix 
 a) for other previous chrome platform.
 b) and split the patch base on each feature.