Change in coreboot[master]: soc/amd/cezanne: enable LPC decodes if platform uses LPC

[Jeremy Soller (Code Review)]

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59103 )

Change subject: soc/amd/cezanne: enable LPC decodes if platform uses LPC
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soc/amd/cezanne: enable LPC decodes if platform uses LPC

Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67
---
M src/soc/amd/cezanne/early_fch.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59103/1

diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index f06d576..8cad78f 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -21,6 +21,12 @@
    I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
 };

+static void lpc_configure_decodes(void)
+{
+	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
+		lpc_enable_port80();
+}
+
 static void reset_i2c_peripherals(void)
 {
    const struct soc_amd_cezanne_config *cfg = config_of_soc();
@@ -41,6 +47,9 @@
    /* Setup SPI base by calling lpc_early_init before setting up eSPI. */
    lpc_early_init();

+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		lpc_configure_decodes();
+
    /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI
       interface hasn't already been set up in verstage on PSP */
    if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))