Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19916 )
Change subject: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings ......................................................................
nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
Change-Id: Icf5bb4a8044bbf2f58c8c9a4774329a95bf3b070 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/19916/1
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 4c15f62..7bfdc6a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1878,6 +1878,11 @@ MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0);
+ if (s->spd_type == DDR3) { + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) + MCHBAR32(0x269 + 0x400 * ch) = MCHBAR32(0x269 + 0x400 * ch) | (1 << 26); + } + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) MCHBAR8(0x260) = MCHBAR8(0x260) | 1;