[S] Change in coreboot[master]: mb/google/brya: Avoid redundant CSE sync

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74806 )

Change subject: mb/google/brya: Avoid redundant CSE sync
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mb/google/brya: Avoid redundant CSE sync

This patch drops the  selection of CSE sync late config
`SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE` from the mainboard directory as
the SoC config will now take care of this feature.

TEST=Able to build google/nissa with this change where CSE sync is
performed early inside ramstage.

Signed-off-by: Subrata Banik 
Change-Id: I6d5dbb45709bedfc343bf59eacebfbb74d804dc6
---
M src/mainboard/google/brya/Kconfig
1 file changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74806/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index eb1790e..2ac76b3 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -84,7 +84,6 @@
    select MEMORY_SOLDERDOWN
    select SOC_INTEL_ALDERLAKE_PCH_N
    select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
-	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
    select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_TI50