Hello Nico Huber,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39984
to review the following change.
Change subject: mb/siemens/field_pg_m6: Do various improvements ......................................................................
mb/siemens/field_pg_m6: Do various improvements
* Select INTEL_GMA_HAVE_VBT
* Add cmos.layout
* Add option to disable VT-d
* Add option to disable HyperThreading
* Move mainboard_init() (GPIO config) to romstage
* Update devicetree wrt. SlotImplemented (WIP)
* Configure EC device enablement Individual bits are based on observation of the original BIOS. For the Chili variant, add a Kconfig option to enable the debug USB port.
* Lock flash early based on CMOS option If the CMOS option `inhibit_flashlock` is _not_ set, enable write- protection and lock the flash down early. This workaround is re- quired as current FSP always locks the SPI interface after PCI enumeration, so we can't enable write-protection when we actually decide to do it (i.e. in the payload).
Change-Id: I8d22ff74a65ca4b1c63e751ee91af3b110aac0ed Signed-off-by: Nico Huber nico.huber@secunet.com Signed-off-by: Felix Singer felix.singer@secunet.com --- M src/mainboard/siemens/field_pg_m6/Kconfig M src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/cmos.layout A src/mainboard/siemens/field_pg_m6/ec.c A src/mainboard/siemens/field_pg_m6/ec.h M src/mainboard/siemens/field_pg_m6/mainboard.c M src/mainboard/siemens/field_pg_m6/romstage.c M src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc M src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb 9 files changed, 261 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39984/1
diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig index aeee917..55e7fef 100644 --- a/src/mainboard/siemens/field_pg_m6/Kconfig +++ b/src/mainboard/siemens/field_pg_m6/Kconfig @@ -9,8 +9,11 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_UART_8250IO if BOARD_SIEMENS_FIELD_PG_M6_BASE + select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION select SOC_INTEL_CANNONLAKE_PCH_H diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc index e957121..bb023f6 100644 --- a/src/mainboard/siemens/field_pg_m6/Makefile.inc +++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc @@ -6,5 +6,8 @@ romstage-y += romstage.c
ramstage-y += mainboard.c +ramstage-y += ec.c + +smm-y += ec.c
subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/field_pg_m6/cmos.layout b/src/mainboard/siemens/field_pg_m6/cmos.layout new file mode 100644 index 0000000..4548540 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/cmos.layout @@ -0,0 +1,61 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 5 hyper_threading +401 1 e 5 vtd + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 5 ethernet1 +441 1 e 1 inhibit_flashlock + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +784 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew +4 0 Disable +4 1 Enable +4 2 Keep +5 0 Disable +5 1 Enable +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/siemens/field_pg_m6/ec.c b/src/mainboard/siemens/field_pg_m6/ec.c new file mode 100644 index 0000000..511c0d4 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/ec.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <timer.h> + +#include "ec.h" + +#define EC_STATUS 0x50 +#define EC_RUNNING (1 << 1) +#define EC_DEVICE_CONTROL_1 0x80 +#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0) +#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1) +#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2) +#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3) +#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6) +#define EC_DEVICE_CONTROL_2 0x81 +#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0) +#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1) +#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2) +#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3) +#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4) +#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5) +#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6) +#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7) + +#define RUNNING_TIMEOUT_MS 3333 + +static bool ec_running(void) +{ + struct stopwatch sw; + uint8_t ec_status; + + stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS); + do + ec_status = ec_read(EC_STATUS); + while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw)); + + if (!(ec_status & EC_RUNNING)) + printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS); + + return !!(ec_status & EC_RUNNING); +} + +void ec_enable_devices(bool enable_usb) +{ + uint8_t control_1, control_2; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON); + control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON; + + control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON); + control_2 |= EC_DEVICE_CONTROL_2_MPI_ON; + if (enable_usb) + control_2 |= EC_DEVICE_CONTROL_2_USB_ON; + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} + +void mainboard_smi_sleep(const uint8_t slp_typ) +{ + uint8_t control_1, control_2; + + if (slp_typ != ACPI_S5) + return; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON); + control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON); + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} diff --git a/src/mainboard/siemens/field_pg_m6/ec.h b/src/mainboard/siemens/field_pg_m6/ec.h new file mode 100644 index 0000000..ca69a42 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SIEMENS_FIELD_PG_M6_EC_H +#define _SIEMENS_FIELD_PG_M6_EC_H + +void ec_enable_devices(bool enable_usb); + +#endif /* _SIEMENS_FIELD_PG_M6_EC_H */ diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c index 508ba22..a61ca2e 100644 --- a/src/mainboard/siemens/field_pg_m6/mainboard.c +++ b/src/mainboard/siemens/field_pg_m6/mainboard.c @@ -3,19 +3,50 @@ * This file is part of the coreboot project. */
+#include <stdint.h> + +#include <arch/acpi.h> +#include <bootstate.h> +#include <console/console.h> #include <device/device.h> -#include <soc/gpio.h> -#include "variant.h" +#include <intelblocks/fast_spi.h> +#include <pc80/mc146818rtc.h>
-static void mainboard_init(void *chip_info) +#include "ec.h" + +static void mainboard_dev_init(struct device *dev) { - const struct pad_config *pads; - size_t num; + const bool enable_usb = CONFIG(BOARD_SIEMENS_FIELD_PG_M6_BASE); + ec_enable_devices(enable_usb); +}
- pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; }
struct chip_operations mainboard_ops = { - .init = mainboard_init, + .enable_dev = mainboard_enable, }; + +static void mainboard_lockdown(void *unused) +{ + u8 inhibit_flashlock = 0; + unsigned int pr; + + get_option(&inhibit_flashlock, "inhibit_flashlock"); + + if (acpi_is_wakeup_s3() || !inhibit_flashlock) { + for (pr = 0; pr < 5; ++pr) { + if (!fast_spi_pr_set_and_lock(pr, 0xffff0000)) + break; + } + if (pr == 5) + die("Failed to find and lock a PR register.\n"); + } else { + inhibit_flashlock = 0; + set_option("inhibit_flashlock", &inhibit_flashlock); + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, mainboard_lockdown, NULL); diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c index 9c2af94..ee31a1b 100644 --- a/src/mainboard/siemens/field_pg_m6/romstage.c +++ b/src/mainboard/siemens/field_pg_m6/romstage.c @@ -3,12 +3,29 @@ * This file is part of the coreboot project. */
+#include <stdint.h> + +#include <option.h> +#include <pc80/mc146818rtc.h> #include <soc/cnl_memcfg_init.h> +#include <soc/gpio.h> #include <soc/romstage.h> #include <spd_bin.h>
+#include "variant.h" + +static void mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { + uint8_t vtd = 1; const struct cnl_mb_cfg cfg = { .spd = { [0] = { READ_SMBUS, { 0x50 << 1 } }, @@ -23,4 +40,10 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); memupd->FspmConfig.EccSupport = 1; memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; + + get_option(&vtd, "vtd"); + memupd->FspmTestConfig.VtdDisable = !vtd; + get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + + mainboard_init(); } diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc index d55796c..c24fb5e 100644 --- a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc +++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project.
-ramstage-y += gpio.c +romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb index 8fd83dd..5ebaae2 100644 --- a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb +++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb @@ -33,6 +33,7 @@ register "PcieRpEnable[0]" = "1" register "PcieRpEnable[5]" = "1" register "PcieRpEnable[16]" = "1" +# register "PcieRpSlotImplemented[16]" = "1"
register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcUsage[5]" = "5"
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39984 )
Change subject: mb/siemens/field_pg_m6: Do various improvements ......................................................................
Abandoned
-
Felix Singer (Code Review)