Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31232
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
soc/amd: Add Merlin Falcon soc code
In preparation to add padmelon to coreboot, add the the code for the soc Merlin Falcon used by padmelon.
BUG=b:none. TEST=Tested later with pasmelon board.
Change-Id: I66cbf4c9a74b7726cbf5d483f6ca3f998442a51f Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/Kconfig A src/soc/amd/merlinfalcon/BiosCallOuts.c A src/soc/amd/merlinfalcon/Kconfig A src/soc/amd/merlinfalcon/Makefile.inc A src/soc/amd/merlinfalcon/acpi.c A src/soc/amd/merlinfalcon/acpi/AmdImc.asl A src/soc/amd/merlinfalcon/acpi/acpi_wake_source.asl A src/soc/amd/merlinfalcon/acpi/cpu.asl A src/soc/amd/merlinfalcon/acpi/globalnvs.asl A src/soc/amd/merlinfalcon/acpi/gpio_lib.asl A src/soc/amd/merlinfalcon/acpi/lpc.asl A src/soc/amd/merlinfalcon/acpi/northbridge.asl A src/soc/amd/merlinfalcon/acpi/pci_int.asl A src/soc/amd/merlinfalcon/acpi/pcie.asl A src/soc/amd/merlinfalcon/acpi/sb_fch.asl A src/soc/amd/merlinfalcon/acpi/sb_pci0_fch.asl A src/soc/amd/merlinfalcon/acpi/sleepstates.asl A src/soc/amd/merlinfalcon/acpi/soc.asl A src/soc/amd/merlinfalcon/acpi/usb.asl A src/soc/amd/merlinfalcon/bootblock/bootblock.c A src/soc/amd/merlinfalcon/chip.c A src/soc/amd/merlinfalcon/chip.h A src/soc/amd/merlinfalcon/cpu.c A src/soc/amd/merlinfalcon/enable_usbdebug.c A src/soc/amd/merlinfalcon/finalize.c A src/soc/amd/merlinfalcon/gpio.c A src/soc/amd/merlinfalcon/hda.c A src/soc/amd/merlinfalcon/i2c.c A src/soc/amd/merlinfalcon/imc.c A src/soc/amd/merlinfalcon/include/soc/acpi.h A src/soc/amd/merlinfalcon/include/soc/amd_pci_int_defs.h A src/soc/amd/merlinfalcon/include/soc/cpu.h A src/soc/amd/merlinfalcon/include/soc/fchec.h A src/soc/amd/merlinfalcon/include/soc/gpio.h A src/soc/amd/merlinfalcon/include/soc/imc.h A src/soc/amd/merlinfalcon/include/soc/iomap.h A src/soc/amd/merlinfalcon/include/soc/northbridge.h A src/soc/amd/merlinfalcon/include/soc/nvs.h A src/soc/amd/merlinfalcon/include/soc/pci_devs.h A src/soc/amd/merlinfalcon/include/soc/romstage.h A src/soc/amd/merlinfalcon/include/soc/smbus.h A src/soc/amd/merlinfalcon/include/soc/smi.h A src/soc/amd/merlinfalcon/include/soc/southbridge.h A src/soc/amd/merlinfalcon/iommu.c A src/soc/amd/merlinfalcon/lpc.c A src/soc/amd/merlinfalcon/mca.c A src/soc/amd/merlinfalcon/monotonic_timer.c A src/soc/amd/merlinfalcon/nb_util.c A src/soc/amd/merlinfalcon/northbridge.c A src/soc/amd/merlinfalcon/pmutil.c A src/soc/amd/merlinfalcon/ramtop.c A src/soc/amd/merlinfalcon/reset.c A src/soc/amd/merlinfalcon/romstage.c A src/soc/amd/merlinfalcon/sata.c A src/soc/amd/merlinfalcon/sb_util.c A src/soc/amd/merlinfalcon/sm.c A src/soc/amd/merlinfalcon/smbus.c A src/soc/amd/merlinfalcon/smbus_spd.c A src/soc/amd/merlinfalcon/smi.c A src/soc/amd/merlinfalcon/smi_util.c A src/soc/amd/merlinfalcon/smihandler.c A src/soc/amd/merlinfalcon/southbridge.c A src/soc/amd/merlinfalcon/spi.c A src/soc/amd/merlinfalcon/tsc_freq.c A src/soc/amd/merlinfalcon/uart.c A src/soc/amd/merlinfalcon/usb.c 66 files changed, 11,686 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31232/1
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31232 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Patch Set 1:
(4 comments)
Ugh. I hate this. It's a complete duplicate of the Stoney tree, changing the names and adding back the IMC code that AMD decided they weren't willing to support. The fact that it's missing the latest stoney changes just shows why it's a bad idea.
Wouldn't it be better to just update the stoney tree to include the few changes that are actually needed?
What's the plan for supporting FP4 AGESA since it's not currently building in the Google codebase?
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/Kconfig File src/soc/amd/merlinfalcon/Kconfig:
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/Kconfig@16 PS1, Line 16: SOC_AMD_MERLINFALCON_FP4 We just closed the bug about AGESA not building for FP4
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/Kconfig@148 PS1, Line 148: MERLINFALCON_ Ugh. Why do we care what chipset it's for? Just make all of these generic in both stoney and Merlinfalcon. It's not like we can enable the stoney controller here. Just use "XHCI_ENABLE". Get rid of all the chipset specific config names that make sense.
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/Kconfig@261 PS1, Line 261: MERLINFALCON_UART Please change to SOC_UART both here and on stoney.
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/include/soc... File src/soc/amd/merlinfalcon/include/soc/smbus.h:
https://review.coreboot.org/#/c/31232/1/src/soc/amd/merlinfalcon/include/soc... PS1, Line 21: : #define SMBHSTSTAT 0x0 : #define SMBHST_STAT_FAILED 0x10 : #define SMBHST_STAT_COLLISION 0x08 : #define SMBHST_STAT_ERROR 0x04 : #define SMBHST_STAT_INTERRUPT 0x02 : #define SMBHST_STAT_BUSY 0x01 : #define SMBHST_STAT_CLEAR 0xff : #define SMBHST_STAT_NOERROR 0x02 : #define SMBHST_STAT_VAL_BITS 0x1f : #define SMBHST_STAT_ERROR_BITS 0x1c : : #define SMBSLVSTAT 0x1 : #define SMBSLV_STAT_ALERT 0x20 : #define SMBSLV_STAT_SHADOW2 0x10 : #define SMBSLV_STAT_SHADOW1 0x08 : #define SMBSLV_STAT_SLV_STS 0x04 : #define SMBSLV_STAT_SLV_INIT 0x02 : #define SMBSLV_STAT_SLV_BUSY 0x01 : #define SMBSLV_STAT_CLEAR 0x1f : : #define SMBHSTCTRL 0x2 : #define SMBHST_CTRL_RST 0x80 : #define SMBHST_CTRL_STRT 0x40 : #define SMBHST_CTRL_QCK_RW 0x00 : #define SMBHST_CTRL_BTE_RW 0x04 : #define SMBHST_CTRL_BDT_RW 0x08 : #define SMBHST_CTRL_WDT_RW 0x0c : #define SMBHST_CTRL_BLK_RW 0x14 : #define SMBHST_CTRL_MODE_BITS 0x1c : #define SMBHST_CTRL_KILL 0x02 : #define SMBHST_CTRL_IEN 0x01 : : #define SMBHSTCMD 0x3 : #define SMBHSTADDR 0x4 : #define SMBHSTDAT0 0x5 : #define SMBHSTDAT1 0x6 : #define SMBHSTBLKDAT 0x7 : #define SMBSLVCTRL 0x8 : #define SMBSLVCMD_SHADOW 0x9 : #define SMBSLVEVT 0xa : #define SMBSLVDAT 0xc : #define SMBTIMING 0xe : : #define SMB_ASF_IO_BASE 0x01 Pull in the latest stoney changes?
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31232 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Patch Set 2:
Still work in progress, just sending review answer back.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31232 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Patch Set 3:
Patch Set 3:
Thank you for pushing this for review. Could you please elaborate in the commit message, where the code comes from (copied), and what blobs are needed for example. Maybe also the differences to Stoney Ridge.
This code will be abandoned soon... it's only still "work in progress" as a way to store work I have already done in case I need to revert to it. A new code using as much of stoneyridge as possible will be submitted. The only difference between stoneneyridge and merlin falcon is the CPU. The first use Bristol with 2 cores, Merlin Falcon uses Carizo with 4 cores. This implies in different VBIOS and PSP, different ID for some devices, and not much else.
Richard Spiegel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31232 )
Change subject: soc/amd: Add Merlin Falcon soc code ......................................................................
Abandoned
New code just modifying stoneyridge is up.
-
Martin Roth (Code Review) -
Richard Spiegel (Code Review)