[XL] Change in coreboot[master]: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP
Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Krishna P Bhat D, Ronak Kanabar, Eric Lai.
Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69396 )
Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP ......................................................................
Patch Set 19:
(5 comments)
File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/69396/comment/b014015b_b4ac2c6b PS18, Line 1: # UPDATEME: Current setting is for VP
what is VP?
Ack
https://review.coreboot.org/c/coreboot/+/69396/comment/eb96e500_5809a39f PS18, Line 34: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C port1
can I have access to the schematics to review this code?
Will come back on this.
https://review.coreboot.org/c/coreboot/+/69396/comment/2a21d10c_4bc3eddf PS18, Line 61: register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_3]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0"
u don't need to set something to zero IMO.
To confirm, Is the suggestion here to skip the initialization of the registers with value 0 ?
File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c:
https://review.coreboot.org/c/coreboot/+/69396/comment/552fb510_86bbf8e2 PS18, Line 10: /* Pad configuration in ramstage*/ : static const struct pad_config mtlmrvp_gpio_table[] = { : /* TODO: Add GPIO configuration for RVP-M */ : };
keep this separate now, please add MTL-P support alone.
Done
https://review.coreboot.org/c/coreboot/+/69396/comment/99f2b416_19be8149 PS18, Line 412: case MTLM_LP5_RVP: : printk(BIOS_DEBUG, "configuring MTLM RVP gpios\n"); : gpio_configure_pads(mtlmrvp_gpio_table, ARRAY_SIZE(mtlmrvp_gpio_table));
same
Done
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Harsha B R (Code Review)