Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 )

Change subject: soc/intel/xeon_sp: Enable SMI handler
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Patch Set 27:
> Patch Set 27:
>
> Arthur,
> Which piece of code is not working for CPU save state? You can also email me directly. [e-mail].  Thx

Coreboot has some code to access the save state per CPU, but makes some assumptions on where that save state is located (smmloaderv1). https://review.coreboot.org/c/coreboot/+/47081/ is a naive attempt on fixing it. Those save state accessors are not used on xeon_sp at the moment so it is not urgent to fix.